diff options
| author | Dan Williams <dan.j.williams@intel.com> | 2023-01-25 15:32:57 -0800 |
|---|---|---|
| committer | Dan Williams <dan.j.williams@intel.com> | 2023-01-25 15:32:57 -0800 |
| commit | 172738bbccdb4ef76bdd72fc72a315c741c39161 (patch) | |
| tree | 2fafe17a1eff9ec82a67067c819b6599e7294a37 /Documentation/ABI/testing/sysfs-bus-cxl | |
| parent | af3ea9ab61d728d5a8be01bbec6d5cf7551b9600 (diff) | |
cxl/port: Link the 'parent_dport' in portX/ and endpointX/ sysfs
Similar to the justification in:
1b58b4cac6fc ("cxl/port: Record parent dport when adding ports")
...userspace wants to know the routing information for ports for
calculating the memdev order for region creation among other things.
Cache the information the kernel discovers at enumeration time in a
'parent_dport' attribute to save userspace the time of trawling sysfs
to recover the same information.
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/167124082375.1626103.6047000000121298560.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'Documentation/ABI/testing/sysfs-bus-cxl')
| -rw-r--r-- | Documentation/ABI/testing/sysfs-bus-cxl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-cxl b/Documentation/ABI/testing/sysfs-bus-cxl index 8494ef27e8d2..329a7e46c805 100644 --- a/Documentation/ABI/testing/sysfs-bus-cxl +++ b/Documentation/ABI/testing/sysfs-bus-cxl @@ -90,6 +90,21 @@ Description: capability. +What: /sys/bus/cxl/devices/{port,endpoint}X/parent_dport +Date: January, 2023 +KernelVersion: v6.3 +Contact: linux-cxl@vger.kernel.org +Description: + (RO) CXL port objects are instantiated for each upstream port in + a CXL/PCIe switch, and for each endpoint to map the + corresponding memory device into the CXL port hierarchy. When a + descendant CXL port (switch or endpoint) is enumerated it is + useful to know which 'dport' object in the parent CXL port + routes to this descendant. The 'parent_dport' symlink points to + the device representing the downstream port of a CXL switch that + routes to {port,endpoint}X. + + What: /sys/bus/cxl/devices/portX/dportY Date: June, 2021 KernelVersion: v5.14 |