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authorSebastian Reichel <sebastian.reichel@collabora.com>2021-08-02 19:23:09 +0200
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2021-08-05 14:29:27 +0200
commit0f920277dc22cb794f0572ee5d3423388453435d (patch)
tree1d228dfe2d9e7e9ee2de9f057e387d5f5aabe30f /Documentation/ABI
parentcd7cd5b716d594e27a933c12f026d4f2426d7bf4 (diff)
misc: gehc-achc: new driver
General Electric Healthcare's PPD has a secondary processor from NXP's Kinetis K20 series. That device has two SPI chip selects: The main interface's behaviour depends on the loaded firmware and is currently unused. The secondary interface can be used to update the firmware using EzPort protocol. This is implemented by this driver using the kernel's firmware API. The firmware is being flashed into non-volatile flash memory, so it is enough to flash it once and not on every boot. Flashing will wear the flash memory (it has a life time of at least 10k programming cycles). At the same time only occasional FW updates are expected (like e.g. a BIOS update). Thus the firmware update is triggered via sysfs instead of doing it in the driver's probe routine like many other drivers. Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Link: https://lore.kernel.org/r/20210802172309.164365-4-sebastian.reichel@collabora.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/ABI')
-rw-r--r--Documentation/ABI/testing/sysfs-driver-ge-achc15
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-driver-ge-achc b/Documentation/ABI/testing/sysfs-driver-ge-achc
new file mode 100644
index 000000000000..a9e7a079190c
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-driver-ge-achc
@@ -0,0 +1,15 @@
+What: /sys/bus/spi/<dev>/update_firmware
+Date: Jul 2021
+Contact: sebastian.reichel@collabora.com
+Description: Write 1 to this file to update the ACHC microcontroller
+ firmware via the EzPort interface. For this the kernel
+ will load "achc.bin" via the firmware API (so usually
+ from /lib/firmware). The write will block until the FW
+ has either been flashed successfully or an error occured.
+
+What: /sys/bus/spi/<dev>/reset
+Date: Jul 2021
+Contact: sebastian.reichel@collabora.com
+Description: This file represents the microcontroller's reset line.
+ 1 means the reset line is asserted, 0 means it's not
+ asserted. The file is read and writable.