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authorGeetha Sowjanya <geethasowjanya.akula@cavium.com>2017-06-23 19:04:36 +0530
committerWill Deacon <will.deacon@arm.com>2017-06-23 17:58:04 +0100
commitf935448acf462c26142e8b04f1c8829b28d3b9d8 (patch)
tree7516f4e4d39117e80be3b2859451725faded8271 /Documentation/arm64/memory.txt
parent99caf177f6fd3e67575f6ce05b36e8e041bcef60 (diff)
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126
Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq lines for gerror, eventq and cmdq-sync. New named irq "combined" is set as a errata workaround, which allows to share the irq line by register single irq handler for all the interrupts. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> [will: reworked irq equality checking and added SPI check] Signed-off-by: Will Deacon <will.deacon@arm.com>
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