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authorGiacomo Travaglini <Giacomo.Travaglini@arm.com>2018-10-01 15:24:47 +0100
committerCatalin Marinas <catalin.marinas@arm.com>2018-10-01 16:28:15 +0100
commit4bfbe5eee309e8c86e1b1155e82136c8fbffd155 (patch)
tree1869fffe553d6af868d2269b93ffd6aea39702bd /Documentation/arm64
parent2ba0dacbae94482e80b00dbd368f0a4aeaabbdec (diff)
arm64: docs: Fix typos in ELF hwcaps
Fix some typos in our hwcap documentation, where we refer to the wrong ID register for some of the capabilities. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> [will: fix amusing binary constants] Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/elf_hwcaps.txt8
1 files changed, 4 insertions, 4 deletions
diff --git a/Documentation/arm64/elf_hwcaps.txt b/Documentation/arm64/elf_hwcaps.txt
index d6aff2c5e9e2..51ccfab408cc 100644
--- a/Documentation/arm64/elf_hwcaps.txt
+++ b/Documentation/arm64/elf_hwcaps.txt
@@ -78,11 +78,11 @@ HWCAP_EVTSTRM
HWCAP_AES
- Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0001.
+ Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0001.
HWCAP_PMULL
- Functionality implied by ID_AA64ISAR1_EL1.AES == 0b0010.
+ Functionality implied by ID_AA64ISAR0_EL1.AES == 0b0010.
HWCAP_SHA1
@@ -153,7 +153,7 @@ HWCAP_ASIMDDP
HWCAP_SHA512
- Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0002.
+ Functionality implied by ID_AA64ISAR0_EL1.SHA2 == 0b0010.
HWCAP_SVE
@@ -173,7 +173,7 @@ HWCAP_USCAT
HWCAP_ILRCPC
- Functionality implied by ID_AA64ISR1_EL1.LRCPC == 0b0002.
+ Functionality implied by ID_AA64ISAR1_EL1.LRCPC == 0b0010.
HWCAP_FLAGM