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authorPaolo Bonzini <pbonzini@redhat.com>2022-05-25 05:09:49 -0400
committerPaolo Bonzini <pbonzini@redhat.com>2022-05-25 05:09:49 -0400
commitb699da3dc27959091fafbd906853a38cfc2887a7 (patch)
treee8e0d4b274876d23ba8b2ec63a12388395fe5246 /Documentation/arm64
parent47e8eec83262083c7da220446551eaad614218ea (diff)
parentfed9b26b2501ea0ce41ae3a788bcc498440589c6 (diff)
Merge tag 'kvm-riscv-5.19-1' of https://github.com/kvm-riscv/linux into HEAD
KVM/riscv changes for 5.19 - Added Sv57x4 support for G-stage page table - Added range based local HFENCE functions - Added remote HFENCE functions based on VCPU requests - Added ISA extension registers in ONE_REG interface - Updated KVM RISC-V maintainers entry to cover selftests support
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/silicon-errata.rst3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst
index 466cb9e89047..d27db84d585e 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -189,6 +189,9 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| Qualcomm Tech. | Kryo4xx Silver | N/A | ARM64_ERRATUM_1024718 |
+----------------+-----------------+-----------------+-----------------------------+
+| Qualcomm Tech. | Kryo4xx Gold | N/A | ARM64_ERRATUM_1286807 |
++----------------+-----------------+-----------------+-----------------------------+
+
+----------------+-----------------+-----------------+-----------------------------+
| Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010001 |
+----------------+-----------------+-----------------+-----------------------------+