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| author | Channagoud Kadabi <ckadabi@codeaurora.org> | 2018-09-12 11:06:34 -0700 |
|---|---|---|
| committer | Andy Gross <andy.gross@linaro.org> | 2018-09-13 15:54:05 -0500 |
| commit | 27450653f1db0b9d5b5048a246c850c52ee4aa61 (patch) | |
| tree | 19e4535d7999ee456f897a33cf2bb293a1c92b54 /Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | |
| parent | c081f3060fab316fcf103967a24e502d58488849 (diff) | |
drivers: edac: Add EDAC driver support for QCOM SoCs
Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
Errors (DBEs). As of now, this driver supports error reporting for
Last Level Cache Controller (LLCC) of Tag RAM and Data RAM. Interrupts
are triggered when the errors happen in the cache, the driver handles
those interrupts and dumps the syndrome registers.
Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Acked-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt')
0 files changed, 0 insertions, 0 deletions