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| author | Maxime Ripard <maxime@cerno.tech> | 2022-04-05 11:37:03 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime@cerno.tech> | 2022-04-05 11:37:03 +0200 |
| commit | cf5c5763eb531ff5120111ad300126e926fb5a56 (patch) | |
| tree | 41e3d49ad46f08fd6025264451390c7dc204303a /Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml | |
| parent | 8047f98c8958d0f0c29882298ec293ff09ffea92 (diff) | |
| parent | 3123109284176b1532874591f7c81f3837bbdc17 (diff) | |
Merge drm/drm-fixes into drm-misc-fixes
Let's start the 5.18 fixes cycle.
Signed-off-by: Maxime Ripard <maxime@cerno.tech>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml index 228c9313df53..f0f9392470a6 100644 --- a/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml +++ b/Documentation/devicetree/bindings/clock/bitmain,bm1880-clk.yaml @@ -61,16 +61,4 @@ examples: #clock-cells = <1>; }; - # Example UART controller node that consumes clock generated by the clock controller: - - | - uart0: serial@58018000 { - compatible = "snps,dw-apb-uart"; - reg = <0x58018000 0x2000>; - clocks = <&clk 45>, <&clk 46>; - clock-names = "baudclk", "apb_pclk"; - interrupts = <0 9 4>; - reg-shift = <2>; - reg-io-width = <4>; - }; - ... |