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authorTomeu Vizoso <tomeu.vizoso@collabora.com>2015-03-12 15:47:59 +0100
committerThierry Reding <treding@nvidia.com>2015-05-13 15:17:10 +0200
commitef03b35a9a2cadd6b3abc758dab4c580a454760c (patch)
tree91707d4725d7b269df6b6a3b6d31fbc28ee2d226 /Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
parente34812c5bac8de641a2551b5ccb601627c10e772 (diff)
of: document external-memory-controller property in tegra124-car
This property contains a phandle to the EMC driver that is needed by the EMC clock to request the EMC driver to do its part of the clock change sequence. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt')
-rw-r--r--Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt2
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
index c3891cece73f..7f02fb4ca4ad 100644
--- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
+++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
@@ -20,6 +20,7 @@ Required properties :
- #reset-cells : Should be 1.
In clock consumers, this cell represents the bit number in the CAR's
array of CLK_RST_CONTROLLER_RST_DEVICES_* registers.
+- nvidia,external-memory-controller : phandle of the EMC driver.
The node should contain a "emc-timings" subnode for each supported RAM type (see
field RAM_CODE in register PMC_STRAPPING_OPT_A).
@@ -50,6 +51,7 @@ Example SoC include file:
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
+ nvidia,external-memory-controller = <&emc>;
};
usb@c5004000 {