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authorBharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>2022-05-16 15:52:17 +0530
committerRob Herring <robh@kernel.org>2022-06-01 14:55:18 -0500
commite2c6170a55baefcbeb477e06e66f07659ea4f58d (patch)
tree977cb14c182f51a5a732d4eacd35c7d86019b014 /Documentation/devicetree/bindings/clock/qcom,mmcc.yaml
parent0a1e19c8a639545ab5912913aba2dd3893cf72fa (diff)
dt-bindings: PCI: xilinx-cpm: Fix reg property order
All existing vendor DTSes are using "cpm_slcr" reg followed by "cfg" reg. This order is also suggested by node name which is pcie@fca10000 which suggests that cpm_slcr register should be the first. Driver itself is using devm_platform_ioremap_resource_byname() for both names that's why there is no functional change even on description which are using current order. But still prefer to change order to cover currently used description. Fixes: e22fadb1d014 ("PCI: xilinx-cpm: Add YAML schemas for Versal CPM Root Port") Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Reviewed-by: Michal Simek <michal.simek@amd.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220516102217.25960-1-bharat.kumar.gogada@xilinx.com
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