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author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2015-05-08 23:31:57 +0900 |
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committer | Yoshinori Sato <ysato@users.sourceforge.jp> | 2015-06-23 13:35:55 +0900 |
commit | 7b5bb891a6e44bd18bd8661ede2e09ccae258ef5 (patch) | |
tree | bf056a4137d4c3cc58e11107c2bdc7393df13ff2 /Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt | |
parent | 8dbdef22d5a720e66ac3939d4c4f7004ef9dd7b4 (diff) |
h8300: clock driver
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt')
-rw-r--r-- | Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt new file mode 100644 index 000000000000..36c2b528245c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,h8300-div-clock.txt @@ -0,0 +1,24 @@ +* Renesas H8/300 divider clock + +Required Properties: + + - compatible: Must be "renesas,sh73a0-h8300-div-clock" + + - clocks: Reference to the parent clocks ("extal1" and "extal2") + + - #clock-cells: Must be 1 + + - reg: Base address and length of the divide rate selector + + - renesas,width: bit width of selector + +Example +------- + + cclk: cclk { + compatible = "renesas,h8300-div-clock"; + clocks = <&xclk>; + #clock-cells = <0>; + reg = <0xfee01b 2>; + renesas,width = <2>; + }; |