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authorLinus Torvalds <torvalds@linux-foundation.org>2020-01-30 07:47:58 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2020-01-30 07:47:58 -0800
commit893e591b59036f9bc629f55bce715d67bdd266a2 (patch)
tree8f52583958252b2b89d86c0d4d94d9cb44f8a4ee /Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.txt
parent1c715a659a16e193a23051ddff4becdad8e18ba1 (diff)
parente9a3bfe38e393e1d8bd74986cdc9b99b8f9d1efc (diff)
Merge tag 'devicetree-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring: - Update dtc to upstream v1.5.1-22-gc40aeb60b47a (plus 1 revert) - Fix for DMA coherent devices on Power - Rework and simplify the DT phandle cache code - DT schema conversions for LEDS, gpio-leds, STM32 dfsdm, STM32 UART, STM32 ROMEM, STM32 watchdog, STM32 DMAs, STM32 mlahb, STM32 RTC, STM32 RCC, STM32 syscon, rs485, Renesas rCar CSI2, Faraday FTIDE010, DWC2, Arm idle-states, Allwinner legacy resets, PRCM and clocks, Allwinner H6 OPP, Allwinner AHCI, Allwinner MBUS, Allwinner A31 CSI, Allwinner h/w codec, Allwinner A10 system ctrl, Allwinner SRAM, Allwinner USB PHY, Renesas CEU, generic PCI host, Arm Versatile PCI - New binding schemas for SATA and PATA controllers, TI and Infineon VR controllers, MAX31730 - New compatible strings for i.MX8QM, WCN3991, renesas,r8a77961-wdt, renesas,etheravb-r8a77961 - Add USB 'super-speed-plus' as a documented speed - Vendor prefixes for broadmobi, calaosystems, kam, and mps - Clean-up the multiple flavors of ST-Ericsson vendor prefixes * tag 'devicetree-for-5.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (66 commits) scripts/dtc: Revert "yamltree: Ensure consistent bracketing of properties with phandles" of: Add OF_DMA_DEFAULT_COHERENT & select it on powerpc dt-bindings: leds: Convert gpio-leds to DT schema dt-bindings: leds: Convert common LED binding to schema dt-bindings: PCI: Convert generic host binding to DT schema dt-bindings: PCI: Convert Arm Versatile binding to DT schema dt-bindings: Be explicit about installing deps dt-bindings: stm32: convert dfsdm to json-schema dt-bindings: serial: Convert STM32 UART to json-schema dt-bindings: serial: Convert rs485 bindings to json-schema dt-bindings: timer: Use non-empty ranges in example dt-bindings: arm-boards: typo fix dt-bindings: Add TI and Infineon VR Controllers as trivial devices dt-binding: usb: add "super-speed-plus" dt-bindings: rcar-csi2: Convert bindings to json-schema dt-bindings: iio: adc: ad7606: Fix wrong maxItems value dt-bindings: Convert Faraday FTIDE010 to DT schema dt-bindings: Create DT bindings for PATA controllers dt-bindings: Create DT bindings for SATA controllers dt: bindings: add vendor prefix for Kamstrup A/S ...
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-STMicroelectronics STM32 Peripheral Reset Clock Controller
-==========================================================
-
-The RCC IP is both a reset and a clock controller.
-
-RCC makes also power management (resume/supend and wakeup interrupt).
-
-Please also refer to reset.txt for common reset controller binding usage.
-
-Please also refer to clock-bindings.txt for common clock controller
-binding usage.
-
-
-Required properties:
-- compatible: "st,stm32mp1-rcc", "syscon"
-- reg: should be register base and length as documented in the datasheet
-- #clock-cells: 1, device nodes should specify the clock in their
- "clocks" property, containing a phandle to the clock device node,
- an index specifying the clock to use.
-- #reset-cells: Shall be 1
-- interrupts: Should contain a general interrupt line and a interrupt line
- to the wake-up of processor (CSTOP).
-
-Example:
- rcc: rcc@50000000 {
- compatible = "st,stm32mp1-rcc", "syscon";
- reg = <0x50000000 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- interrupts = <GIC_SPI 5 IRQ_TYPE_NONE>,
- <GIC_SPI 145 IRQ_TYPE_NONE>;
- };
-
-Specifying clocks
-=================
-
-All available clocks are defined as preprocessor macros in
-dt-bindings/clock/stm32mp1-clks.h header and can be used in device
-tree sources.
-
-Specifying softreset control of devices
-=======================================
-
-Device nodes should specify the reset channel required in their "resets"
-property, containing a phandle to the reset device node and an index specifying
-which channel to use.
-The index is the bit number within the RCC registers bank, starting from RCC
-base address.
-It is calculated as: index = register_offset / 4 * 32 + bit_offset.
-Where bit_offset is the bit offset within the register.
-
-For example on STM32MP1, for LTDC reset:
- ltdc = APB4_RSTSETR_offset / 4 * 32 + LTDC_bit_offset
- = 0x180 / 4 * 32 + 0 = 3072
-
-The list of valid indices for STM32MP1 is available in:
-include/dt-bindings/reset-controller/stm32mp1-resets.h
-
-This file implements defines like:
-#define LTDC_R 3072