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authorGabriel Fernandez <gabriel.fernandez@linaro.org>2015-06-23 16:09:00 +0200
committerMaxime Coquelin <maxime.coquelin@st.com>2015-07-22 11:41:33 +0200
commit5eb26c60590983e11f567916a83d1f0a70986553 (patch)
tree4c3073dc88c4bfc9fcf1982cee21513ca636fbc0 /Documentation/devicetree/bindings/clock/st
parent0a8c739c066254195b86bc8387fe16e5f72a5bdd (diff)
ARM: STi: DT: Rename st_pll3200c32_407_c0_x into st_pll3200c32_cx_x
Use a generic name for this kind of PLL Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/st')
-rw-r--r--Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
index efb51cf0c845..d8b168ebd5f1 100644
--- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
+++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt
@@ -21,8 +21,8 @@ Required properties:
"st,stih416-plls-c32-ddr", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a0", "st,clkgen-plls-c32"
"st,stih407-plls-c32-a9", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32"
- "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_0", "st,clkgen-plls-c32"
+ "sst,plls-c32-cx_1", "st,clkgen-plls-c32"
"st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32"
"st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32"