diff options
| author | Gabriel Fernandez <gabriel.fernandez@linaro.org> | 2015-10-07 11:08:58 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@codeaurora.org> | 2015-10-08 23:52:59 -0700 |
| commit | 0829ea5af6d3338c3c5ad0bd377d75a30d6ffc8b (patch) | |
| tree | 4dca0c232d6d48cdd98415ff0c8e46bc167d3563 /Documentation/devicetree/bindings/clock/st | |
| parent | 46a57afdd70c17cf15b2077c5ea611913f80f85f (diff) | |
drivers: clk: st: Correct the pll-type for A9 for stih418
Add support for new PLL-type for stih418 A9-PLL.
Currently the 407_A9_PLL type being used, it is corrected with this patch
4600c28 PLL allows to reach higher frequencies
so its programming algorithm is extended.
Signed-off-by: Pankaj Dev <pankaj.dev@st.com>
Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/st')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index d8b168ebd5f1..844b3a0976bf 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -23,6 +23,7 @@ Required properties: "st,stih407-plls-c32-a9", "st,clkgen-plls-c32" "sst,plls-c32-cx_0", "st,clkgen-plls-c32" "sst,plls-c32-cx_1", "st,clkgen-plls-c32" + "st,stih418-plls-c28-a9", "st,clkgen-plls-c32" "st,stih415-gpu-pll-c32", "st,clkgengpu-pll-c32" "st,stih416-gpu-pll-c32", "st,clkgengpu-pll-c32" |