diff options
| author | Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> | 2023-08-02 10:05:57 +0530 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2023-08-02 12:12:09 -0700 |
| commit | 03d4a1004053ad78f5928f3e869c2df29d25f541 (patch) | |
| tree | c038913cea181be331e6a0545ceaefbcf69135a3 /Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | |
| parent | 172044e30b00977784269e8ab72132a48293c654 (diff) | |
dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml
Convert the xlnx,zynqmp-clk.txt to yaml.
versal-clk.yaml already exists that's why ZynqMP is converted and
merged.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Link: https://lore.kernel.org/r/20230802043557.26478-1-shubhrajyoti.datta@amd.com
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 80 |
1 files changed, 71 insertions, 9 deletions
diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 04ea327d5313..1ba687d433b1 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -17,7 +17,9 @@ description: | properties: compatible: oneOf: - - const: xlnx,versal-clk + - enum: + - xlnx,versal-clk + - xlnx,zynqmp-clk - items: - enum: - xlnx,versal-net-clk @@ -29,16 +31,12 @@ properties: clocks: description: List of clock specifiers which are external input clocks to the given clock controller. - items: - - description: reference clock - - description: alternate reference clock - - description: alternate reference clock for programmable logic + minItems: 3 + maxItems: 8 clock-names: - items: - - const: ref - - const: alt_ref - - const: pl_alt_ref + minItems: 3 + maxItems: 8 required: - compatible @@ -48,6 +46,61 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - xlnx,versal-clk + + then: + properties: + clocks: + items: + - description: reference clock + - description: alternate reference clock + - description: alternate reference clock for programmable logic + + clock-names: + items: + - const: ref + - const: alt_ref + - const: pl_alt_ref + + - if: + properties: + compatible: + contains: + enum: + - xlnx,zynqmp-clk + + then: + properties: + clocks: + minItems: 5 + items: + - description: PS reference clock + - description: reference clock for video system + - description: alternative PS reference clock + - description: auxiliary reference clock + - description: transceiver reference clock + - description: (E)MIO clock source (Optional clock) + - description: GEM emio clock (Optional clock) + - description: Watchdog external clock (Optional clock) + + clock-names: + minItems: 5 + items: + - const: pss_ref_clk + - const: video_clk + - const: pss_alt_ref_clk + - const: aux_ref_clk + - const: gt_crx_ref_clk + - pattern: "^mio_clk[00-77]+.*$" + - pattern: "gem[0-3]+_emio_clk.*$" + - pattern: "swdt[0-1]+_ext_clk.*$" + examples: - | firmware { @@ -62,4 +115,13 @@ examples: }; }; }; + + clock-controller { + #clock-cells = <1>; + compatible = "xlnx,zynqmp-clk"; + clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, + <&aux_ref_clk>, <>_crx_ref_clk>; + clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk", + "aux_ref_clk", "gt_crx_ref_clk"; + }; ... |