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| author | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-12-21 12:02:29 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2018-01-04 20:01:47 +0100 |
| commit | 71b03a96ffe24bd295fff3197ff7f5fc230ce2e2 (patch) | |
| tree | eed2e7371068a0f074f00ce7e87e5666fffc0d81 /Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | |
| parent | 5b8ea816e8e057702d8c2ac66342c864fa517ede (diff) | |
dt-bindings: display: sun4i-drm: Add LVDS properties
Some clocks and resets supposed to drive the LVDS logic in the display
engine have been overlooked when the driver was first introduced.
Add those additional resources to the binding, and we'll deal with the ABI
stability in the code.
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ddbde28fe2e4f21412974e4c69fbfe1c5ff9383f.1513854122.git-series.maxime.ripard@free-electrons.com
Diffstat (limited to 'Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index 50cc72ee1168..238876cef077 100644 --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt @@ -121,6 +121,14 @@ Required properties: On SoCs other than the A33 and V3s, there is one more clock required: - 'tcon-ch1': The clock driving the TCON channel 1 +On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you +need one more reset line: + - 'lvds': The reset line driving the LVDS logic + +And on the A23, A31, A31s and A33, you need one more clock line: + - 'lvds-alt': An alternative clock source, separate from the TCON channel 0 + clock, that can be used to drive the LVDS clock + DRC --- |