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authorMaxime Ripard <maxime.ripard@free-electrons.com>2017-02-01 09:53:22 +0100
committerMaxime Ripard <maxime.ripard@free-electrons.com>2017-02-02 11:50:18 +0100
commit487a07fba0c9755864283c6c79d7ea86e811070a (patch)
tree23658bf8fb0dfbd97b55854ac2c625b0d65dd3e6 /Documentation/devicetree/bindings/gpu
parentef09e0f539f124c67aa44d4154730bc8492196bf (diff)
dt-bindings: gpu: Add Mali Utgard bindings
The ARM Mali Utgard GPU family is embedded into a number of SoCs from Allwinner, Amlogic, Mediatek or Rockchip. Add a binding for the GPU of that family. Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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+ARM Mali Utgard GPU
+===================
+
+Required properties:
+ - compatible
+ * Must be one of the following:
+ + "arm,mali-300"
+ + "arm,mali-400"
+ + "arm,mali-450"
+ * And, optionally, one of the vendor specific compatible:
+ + allwinner,sun4i-a10-mali
+ + allwinner,sun7i-a20-mali
+ + amlogic,meson-gxbb-mali
+ + amlogic,meson-gxl-mali
+ + stericsson,db8500-mali
+
+ - reg: Physical base address and length of the GPU registers
+
+ - interrupts: an entry for each entry in interrupt-names.
+ See ../interrupt-controller/interrupts.txt for details.
+
+ - interrupt-names:
+ * ppX: Pixel Processor X interrupt (X from 0 to 7)
+ * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
+ * pp: Pixel Processor broadcast interrupt (mali-450 only)
+ * gp: Geometry Processor interrupt
+ * gpmmu: Geometry Processor MMU interrupt
+
+ - clocks: an entry for each entry in clock-names
+ - clock-names:
+ * bus: bus clock for the GPU
+ * core: clock driving the GPU itself
+
+Optional properties:
+ - interrupt-names and interrupts:
+ * pmu: Power Management Unit interrupt, if implemented in hardware
+
+Vendor-specific bindings
+------------------------
+
+The Mali GPU is integrated very differently from one SoC to
+another. In order to accomodate those differences, you have the option
+to specify one more vendor-specific compatible, among:
+
+ - allwinner,sun4i-a10-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - allwinner,sun7i-a20-mali
+ Required properties:
+ * resets: phandle to the reset line for the GPU
+
+ - stericsson,db8500-mali
+ Required properties:
+ * interrupt-names and interrupts:
+ + combined: combined interrupt of all of the above lines
+
+Example:
+
+mali: gpu@1c40000 {
+ compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
+ reg = <0x01c40000 0x10000>;
+ interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp",
+ "gpmmu",
+ "pp0",
+ "ppmmu0",
+ "pp1",
+ "ppmmu1",
+ "pmu";
+ clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
+ clock-names = "bus", "core";
+ resets = <&ccu RST_BUS_GPU>;
+};
+