diff options
| author | Dmitry Osipenko <digetx@gmail.com> | 2021-03-31 02:04:41 +0300 |
|---|---|---|
| committer | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-04-01 19:58:22 +0200 |
| commit | 7885db0ce77426df8bc82bb71d295263772afc3e (patch) | |
| tree | 3d378cb62783863a7da25a23cccb77d78abfa056 /Documentation/devicetree/bindings/memory-controllers | |
| parent | 4be3973c001ee627d220037d2be67a8e39cecc66 (diff) | |
dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet, and thus, it's okay to change it.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210330230445.26619-3-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Diffstat (limited to 'Documentation/devicetree/bindings/memory-controllers')
| -rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml index 0a2e2c0d0fdd..fb6af14cb49c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml @@ -39,9 +39,10 @@ properties: description: Phandle of the Memory Controller node. - core-supply: + power-domains: + maxItems: 1 description: - Phandle of voltage regulator of the SoC "core" power domain. + Phandle of the SoC "core" power domain. operating-points-v2: description: @@ -241,7 +242,7 @@ examples: nvidia,memory-controller = <&mc>; operating-points-v2 = <&dvfs_opp_table>; - core-supply = <&vdd_core>; + power-domains = <&domain>; #interconnect-cells = <0>; |