diff options
| author | Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com> | 2023-06-30 19:52:32 +0530 |
|---|---|---|
| committer | Tudor Ambarus <tudor.ambarus@linaro.org> | 2023-07-13 05:27:02 +0300 |
| commit | cfc2928cb213d5c20b6313abb2d603c0c60d7637 (patch) | |
| tree | a6bf0e437305851e21988a4b1883fac54d33d374 /Documentation/devicetree/bindings/mtd | |
| parent | 06c2afb862f9da8dc5efa4b6076a0e48c3fbaaa5 (diff) | |
dt-bindings: mtd: jedec, spi-nor: Add DT property to avoid setting SRWD bit in status register
If the WP# signal of the flash device is either not connected or is wrongly
tied to GND (that includes internal pull-downs), and the software sets the
status register write disable (SRWD) bit in the status register then the
status register permanently becomes read-only. To avoid this added a new
boolean DT property "no-wp". If this property is set in the DT then the
software avoids setting the SRWD during status register write operation.
Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@amd.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Michael Walle <michael@walle.cc>
Link: https://lore.kernel.org/r/20230630142233.63585-2-amit.kumar-mahapatra@amd.com
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/mtd')
| -rw-r--r-- | Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml index 89959e5c47ba..97344969b02d 100644 --- a/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml +++ b/Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml @@ -70,6 +70,21 @@ properties: be used on such systems, to denote the absence of a reliable reset mechanism. + no-wp: + type: boolean + description: + The status register write disable (SRWD) bit in status register, combined + with the WP# signal, provides hardware data protection for the device. When + the SRWD bit is set to 1, and the WP# signal is either driven LOW or hard + strapped to LOW, the status register nonvolatile bits become read-only and + the WRITE STATUS REGISTER operation will not execute. The only way to exit + this hardware-protected mode is to drive WP# HIGH. If the WP# signal of the + flash device is not connected or is wrongly tied to GND (that includes internal + pull-downs) then status register permanently becomes read-only as the SRWD bit + cannot be reset. This boolean flag can be used on such systems to avoid setting + the SRWD bit while writing the status register. WP# signal hard strapped to GND + can be a valid use case. + reset-gpios: description: A GPIO line connected to the RESET (active low) signal of the device. |