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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-01-18 10:18:55 +0000
committerRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2022-01-18 10:18:55 +0000
commit51efd61e20a08e1a262c3b8b6219600ebca2006c (patch)
tree887b7604bffd071d5a07640040cc8c9d7f7b09a6 /Documentation/devicetree/bindings/net/marvell,10g.yaml
parent956c86b60ce352b3e195c6f0700a07176989d356 (diff)
parente2365fc3e4a0e134ee7f875ce71f0abaaeb4552d (diff)
Merge branches 'mvebu-cpuidle' and 'mvneta' into clearfog
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+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/marvell,10g.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Alaska X family Ethernet PHYs
+
+maintainers:
+ - Russell King <rmk+kernel@armlinux.org.uk>
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+properties:
+ marvell,led-mode:
+ description: |
+ An array of one to four 16-bit integers to write to the PHY LED
+ configuration registers.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint16-array
+ - minItems: 1
+ maxItems: 4
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ethernet-phy@0 {
+ reg = <0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ marvell,led-mode = /bits/ 16 <0x0129 0x095d 0x0855>;
+ };
+ };