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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-10-03 11:09:16 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2017-10-03 11:09:16 +0200 |
| commit | 0d3c24e936feefeca854073ccb40613cd6eba9a9 (patch) | |
| tree | 1f675397b924846740b0931b066ddce6f3d7eb3d /Documentation/devicetree/bindings/pci/hisilicon-pcie.txt | |
| parent | 1af0838de60e723cb02253ecc9b555c30f8f6a6f (diff) | |
| parent | ebec44a2456fbe5fe18aae88f6010f6878f0cb4a (diff) | |
Merge airlied/drm-next into drm-misc-next
Just catching up with upstream.
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/hisilicon-pcie.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/hisilicon-pcie.txt | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt index a339dbb15493..bdb7ab39d2d7 100644 --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt @@ -1,7 +1,7 @@ HiSilicon Hip05 and Hip06 PCIe host bridge DT description -HiSilicon PCIe host controller is based on Designware PCI core. -It shares common functions with PCIe Designware core driver and inherits +HiSilicon PCIe host controller is based on the Synopsys DesignWare PCI core. +It shares common functions with the PCIe DesignWare core driver and inherits common properties defined in Documentation/devicetree/bindings/pci/designware-pci.txt. @@ -40,7 +40,6 @@ Hip05 Example (note that Hip06 is the same except compatible): 0x0 0 0 2 &mbigen_pcie 2 11 0x0 0 0 3 &mbigen_pcie 3 12 0x0 0 0 4 &mbigen_pcie 4 13>; - status = "ok"; }; HiSilicon Hip06/Hip07 PCIe host bridge DT (almost-ECAM) description. @@ -83,5 +82,4 @@ Example: 0x0 0 0 2 &mbigen_pcie0 650 4 0x0 0 0 3 &mbigen_pcie0 650 4 0x0 0 0 4 &mbigen_pcie0 650 4>; - status = "ok"; }; |