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| author | Conor Dooley <conor.dooley@microchip.com> | 2022-08-20 00:14:12 +0100 |
|---|---|---|
| committer | Lorenzo Pieralisi <lpieralisi@kernel.org> | 2022-08-24 13:38:26 +0200 |
| commit | 1a7966b33b5bbefd950cffef1ea8ee3f5f1bf076 (patch) | |
| tree | bd24864c65460544b6139d5dab51c74ab61d7617 /Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | |
| parent | 05a5741019a524ab9e1d355528c8ebcbd6debfe7 (diff) | |
dt-bindings: PCI: microchip,pcie-host: fix missing dma-ranges
The dma-ranges property was missed when adding the binding initially.
The root port can use up to 6 address translation tables, depending on
configuration.
Link: https://www.microsemi.com/document-portal/doc_download/1245812-polarfire-fpga-and-polarfire-soc-fpga-pci-express-user-guide # Section 1.3.3
Link: https://lore.kernel.org/r/20220819231415.3860210-4-mail@conchuod.ie
Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding")
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 6fbe62f4da93..23d95c65acff 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -67,6 +67,10 @@ properties: ranges: maxItems: 1 + dma-ranges: + minItems: 1 + maxItems: 6 + msi-controller: description: Identifies the node as an MSI controller. |