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authorEric Yuen <eyuen@nvidia.com>2014-08-26 17:11:37 +0200
committerBjorn Helgaas <bhelgaas@google.com>2014-09-16 16:55:33 -0600
commitec73276204f06b6446a9c9b70173a1c15f6de536 (patch)
treee662f3fd15fe8b9f98e7cbcde7e6bc4227a44823 /Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
parent8d41794c6fc61ac2f09b5c25267e2c68748326cc (diff)
PCI: tegra: Make sure the PCIe PLL is really reset
Depending on the prior state of the controller, the PLL reset may not be pulsed. Clear the register bit and set it after a small delay to ensure that the PLL is really reset. Tested-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Eric Yuen <eyuen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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