diff options
author | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-01 16:35:50 -0500 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2017-09-01 16:35:50 -0500 |
commit | 96291d565550c1fd363e488cc17cb3189d2e4cc2 (patch) | |
tree | 5edda68ba7ef9568df9a8a843a4e5c03be656ed8 /Documentation/devicetree/bindings/pci/rockchip-pcie.txt | |
parent | cacf7eaf2a36cc51c24b591d681676b6d27a7a6e (diff) |
PCI: Fix typos and whitespace errors
Fix various typos and whitespace errors:
s/Synopsis/Synopsys/
s/Designware/DesignWare/
s/Keystine/Keystone/
s/gpio/GPIO/
s/pcie/PCIe/
s/phy/PHY/
s/confgiruation/configuration/
No functional change intended.
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/rockchip-pcie.txt')
-rw-r--r-- | Documentation/devicetree/bindings/pci/rockchip-pcie.txt | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt index 1453a734c2f5..1136e9282108 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-pcie.txt +++ b/Documentation/devicetree/bindings/pci/rockchip-pcie.txt @@ -45,7 +45,7 @@ Required properties: Optional Property: - aspm-no-l0s: RC won't support ASPM L0s. This property is needed if using 24MHz OSC for RC's PHY. -- ep-gpios: contain the entry for pre-reset gpio +- ep-gpios: contain the entry for pre-reset GPIO - num-lanes: number of lanes to use - vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe. - vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe. |