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author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-16 11:24:51 -0700 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-16 11:24:51 -0700 |
commit | 90a498f294c2766f05ba72dbc0ecafb2af521a4c (patch) | |
tree | a63523273c5965ee84ff726617bfcf67a3308b9c /Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | |
parent | 4438a810f3962a65d1d7259ee4195853a4d21a00 (diff) | |
parent | 00ca8a15dafa990d391abc37f2b8256ddf909b35 (diff) |
Merge tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"New hardware support:
- Qualcomm X1E80100 PCIe phy support, SM8550 PCIe1 PHY, SC7180 UFS
PHY and SDM630 USBC support
- Rockchip HDMI/eDP Combo PHY driver
- Mediatek MT8365 CSI phy driver
Updates:
- Rework on Qualcomm phy PCS registers and type-c handling
- Cadence torrent phy updates for multilink configuration
- TI gmii resume support"
* tag 'phy-for-6.9' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (41 commits)
phy: constify of_phandle_args in xlate
phy: ti: tusb1210: Define device IDs
phy: ti: tusb1210: Use temporary variable for struct device
phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver
dt-bindings: phy: Add Rockchip HDMI/eDP Combo PHY schema
phy: ti: gmii-sel: add resume support
phy: mtk-mipi-csi: add driver for CSI phy
dt-bindings: phy: add mediatek MIPI CD-PHY module v0.5
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink config for TI J7200
dt-bindings: phy: cadence-torrent: Add a separate compatible for TI J7200
phy: cadence-torrent: Add USXGMII(156.25MHz) + SGMII/QSGMII(100MHz) multilink configuration
phy: cadence-torrent: Add PCIe(100MHz) + USXGMII(156.25MHz) multilink configuration
dt-bindings: phy: cadence-torrent: Add optional input reference clock for PLL1
phy: qcom-qmp-ufs: Switch to devm_clk_bulk_get_all() API
dt-bindings: phy: qmp-ufs: Fix PHY clocks
phy: qcom: sgmii-eth: move PCS registers to separate header
phy: qcom: sgmii-eth: use existing register definitions
phy: qcom: qmp-usbc: drop has_pwrdn_delay handling
phy: qcom: qmp: move common bits definitions to common header
phy: qcom: qmp: split DP PHY registers to separate headers
...
Diffstat (limited to 'Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml | 184 |
1 files changed, 184 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml new file mode 100644 index 000000000000..f1f4e4f83352 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,msm8998-qmp-usb3-phy.yaml @@ -0,0 +1,184 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-usb3-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP PHY controller (USB, MSM8998) + +maintainers: + - Vinod Koul <vkoul@kernel.org> + +description: + The QMP PHY controller supports physical layer functionality for USB-C on + several Qualcomm chipsets. + +properties: + compatible: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,qcm2290-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy + - const: phy_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 0 + + clock-output-names: + maxItems: 1 + + "#phy-cells": + const: 0 + + orientation-switch: + description: + Flag the PHY as possible handler of USB Type-C orientation switching + type: boolean + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + description: Clamp register present in the TCSR + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB controller + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - clock-output-names + - "#phy-cells" + - qcom,tcsr-reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-qmp-usb3-phy + - qcom,sdm660-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: aux + - const: ref + - const: cfg_ahb + - const: pipe + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcm2290-qmp-usb3-phy + - qcom,sm6115-qmp-usb3-phy + then: + properties: + clocks: + maxItems: 4 + clock-names: + items: + - const: cfg_ahb + - const: ref + - const: com_aux + - const: pipe + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/clock/qcom,rpmh.h> + + phy@c010000 { + compatible = "qcom,msm8998-qmp-usb3-phy"; + reg = <0x0c010000 0x1000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_CLKREF_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "cfg_ahb", + "pipe"; + clock-output-names = "usb3_phy_pipe_clk_src"; + #clock-cells = <0>; + #phy-cells = <0>; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy", + "phy_phy"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; + + orientation-switch; + + qcom,tcsr-reg = <&tcsr_regs_1 0x6b244>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&pmic_typec_mux_in>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&usb_dwc3_ss>; + }; + }; + }; + }; |