diff options
| author | Iskren Chernev <iskren.chernev@gmail.com> | 2020-09-22 14:42:35 +0300 |
|---|---|---|
| committer | Sebastian Reichel <sebastian.reichel@collabora.com> | 2020-10-03 19:18:28 +0200 |
| commit | b973c9d518199bd8362aeae13d208d8889283287 (patch) | |
| tree | 7fe6356cfd34a5d0cc3b8a7ab91ea9555dda2b6a /Documentation/devicetree/bindings/power | |
| parent | 4f7f8e87c49e029a52318dd76d561860119d0372 (diff) | |
dt-bindings: power: supply: max17040: Add maxim,rcomp
To compensate for the battery chemistry and operating conditions the
chips support a compensation value. Specify one or two byte compensation
via the maxim,rcomp byte array.
Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Diffstat (limited to 'Documentation/devicetree/bindings/power')
| -rw-r--r-- | Documentation/devicetree/bindings/power/supply/max17040_battery.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/power/supply/max17040_battery.txt b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt index 5aa83e797a02..c802f664b508 100644 --- a/Documentation/devicetree/bindings/power/supply/max17040_battery.txt +++ b/Documentation/devicetree/bindings/power/supply/max17040_battery.txt @@ -17,6 +17,11 @@ Optional properties : Specify this boolean property to divide the reported value in 2 and thus normalize it. SOC == State of Charge == Capacity. +- maxim,rcomp : A value to compensate readings for various + battery chemistries and operating temperatures. + max17040,41 have 2 byte rcomp, default to + 0x97 0x00. All other devices have one byte + rcomp, default to 0x97. - interrupts : Interrupt line see Documentation/devicetree/ bindings/interrupt-controller/interrupts.txt - wakeup-source : This device has wakeup capabilities. Use this @@ -41,6 +46,7 @@ Example: battery-fuel-gauge@36 { compatible = "maxim,max17048"; reg = <0x36>; + maxim,rcomp = /bits/ 8 <0x56>; maxim,alert-low-soc-level = <10>; maxim,double-soc; }; |