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author | Grant Likely <grant.likely@secretlab.ca> | 2011-02-12 23:53:34 -0700 |
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committer | Grant Likely <grant.likely@secretlab.ca> | 2011-02-12 23:53:34 -0700 |
commit | c170093d31bd4e3bc51881cc0f123beeca7872c9 (patch) | |
tree | d93cd280d525dd339f33be010c75b7fd0bacd690 /Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt | |
parent | 557218e2d662574bc58d840fe116c7fd8d57aed8 (diff) | |
parent | 78bba987bc025a7263248501b453476e77b93331 (diff) |
Merge branch 'devicetree/merge' into spi/merge
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt')
-rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt new file mode 100644 index 000000000000..349f79fd7076 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpm_qe/gpio.txt @@ -0,0 +1,38 @@ +Every GPIO controller node must have #gpio-cells property defined, +this information will be used to translate gpio-specifiers. + +On CPM1 devices, all ports are using slightly different register layouts. +Ports A, C and D are 16bit ports and Ports B and E are 32bit ports. + +On CPM2 devices, all ports are 32bit ports and use a common register layout. + +Required properties: +- compatible : "fsl,cpm1-pario-bank-a", "fsl,cpm1-pario-bank-b", + "fsl,cpm1-pario-bank-c", "fsl,cpm1-pario-bank-d", + "fsl,cpm1-pario-bank-e", "fsl,cpm2-pario-bank" +- #gpio-cells : Should be two. The first cell is the pin number and the + second cell is used to specify optional parameters (currently unused). +- gpio-controller : Marks the port as GPIO controller. + +Example of three SOC GPIO banks defined as gpio-controller nodes: + + CPM1_PIO_A: gpio-controller@950 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-a"; + reg = <0x950 0x10>; + gpio-controller; + }; + + CPM1_PIO_B: gpio-controller@ab8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-b"; + reg = <0xab8 0x10>; + gpio-controller; + }; + + CPM1_PIO_E: gpio-controller@ac8 { + #gpio-cells = <2>; + compatible = "fsl,cpm1-pario-bank-e"; + reg = <0xac8 0x18>; + gpio-controller; + }; |