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author | Jiri Kosina <jkosina@suse.cz> | 2013-05-28 12:01:07 +0200 |
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committer | Jiri Kosina <jkosina@suse.cz> | 2013-05-28 12:01:07 +0200 |
commit | 6e9041c6ddd6cbdc61d87bcaca8ca7bb17c28377 (patch) | |
tree | c250644c5adce04947d664318996de16df3f02da /Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | |
parent | b96516220870d8571fc12da980668687c122976e (diff) | |
parent | e4aa937ec75df0eea0bee03bffa3303ad36c986b (diff) |
Merge branch 'master' into for-next
Diffstat (limited to 'Documentation/devicetree/bindings/powerpc/fsl/cpus.txt')
-rw-r--r-- | Documentation/devicetree/bindings/powerpc/fsl/cpus.txt | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt new file mode 100644 index 000000000000..922c30ad90d1 --- /dev/null +++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt @@ -0,0 +1,22 @@ +=================================================================== +Power Architecture CPU Binding +Copyright 2013 Freescale Semiconductor Inc. + +Power Architecture CPUs in Freescale SOCs are represented in device trees as +per the definition in ePAPR. + +In addition to the ePAPR definitions, the properties defined below may be +present on CPU nodes. + +PROPERTIES + + - fsl,eref-* + Usage: optional + Value type: <empty> + Definition: The EREF (EREF: A Programmer.s Reference Manual for + Freescale Power Architecture) defines the architecture for Freescale + Power CPUs. The EREF defines some architecture categories not defined + by the Power ISA. For these EREF-specific categories, the existence of + a property named fsl,eref-[CAT], where [CAT] is the abbreviated category + name with all uppercase letters converted to lowercase, indicates that + the category is supported by the implementation. |