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authorJia Jie Ho <jiajie.ho@starfivetech.com>2023-01-17 09:54:43 +0800
committerHerbert Xu <herbert@gondor.apana.org.au>2023-01-27 18:57:24 +0800
commita482b02d6ae0d82c3c616ec0fb2a7b3080707e48 (patch)
treeeae658175efbd3300b04f69c4ca83193f37b7d7d /Documentation/devicetree/bindings/rng
parent4fc790d7d6b15eb4b90d297eb8c93589748e0c49 (diff)
dt-bindings: rng: Add StarFive TRNG module
Add documentation to describe Starfive true random number generator module. Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Diffstat (limited to 'Documentation/devicetree/bindings/rng')
-rw-r--r--Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml55
1 files changed, 55 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
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index 000000000000..2b76ce25acc4
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+++ b/Documentation/devicetree/bindings/rng/starfive,jh7110-trng.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rng/starfive,jh7110-trng.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive SoC TRNG Module
+
+maintainers:
+ - Jia Jie Ho <jiajie.ho@starfivetech.com>
+
+properties:
+ compatible:
+ const: starfive,jh7110-trng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Hardware reference clock
+ - description: AHB reference clock
+
+ clock-names:
+ items:
+ - const: hclk
+ - const: ahb
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ rng: rng@1600C000 {
+ compatible = "starfive,jh7110-trng";
+ reg = <0x1600C000 0x4000>;
+ clocks = <&clk 15>, <&clk 16>;
+ clock-names = "hclk", "ahb";
+ resets = <&reset 3>;
+ interrupts = <30>;
+ };
+...