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authorBjorn Helgaas <bhelgaas@google.com>2019-05-13 18:34:41 -0500
committerBjorn Helgaas <bhelgaas@google.com>2019-05-13 18:34:41 -0500
commit0b8439d374826f03d47b995bd5950ea8d8b7cff8 (patch)
tree3e0be2b0e8cab9629d7cd0f050c38f232abd1b78 /Documentation/devicetree
parentb138f67d7badf9ecb08c120e9c9ecbb8d483da59 (diff)
parent8f220664570e755946db1282f48e07f26e1f2cb4 (diff)
Merge branch 'remotes/lorenzo/pci/keystone'
- Move IRQ register address computation inside macros (Kishon Vijay Abraham I) - Separate legacy IRQ and MSI configuration (Kishon Vijay Abraham I) - Use hwirq, not virq, to get MSI IRQ number offset (Kishon Vijay Abraham I) - Squash ks_pcie_handle_msi_irq() into ks_pcie_msi_irq_handler() (Kishon Vijay Abraham I) - Add dwc support for platforms with custom MSI controllers (Kishon Vijay Abraham I) - Add keystone-specific MSI controller (Kishon Vijay Abraham I) - Remove dwc host_ops previously used for keystone-specific MSI (Kishon Vijay Abraham I) - Skip dwc default MSI init if platform has custom MSI controller (Kishon Vijay Abraham I) - Implement .start_link() and .stop_link() for keystone endpoint support (Kishon Vijay Abraham I) - Add keystone "reg-names" DT binding (Kishon Vijay Abraham I) - Squash ks_pcie_dw_host_init() into ks_pcie_add_pcie_port() (Kishon Vijay Abraham I) - Get keystone register resources from DT by name, not index (Kishon Vijay Abraham I) - Get DT resources in .probe() to prepare for endpoint support (Kishon Vijay Abraham I) - Add "ti,syscon-pcie-mode" DT property for PCIe mode configuration (Kishon Vijay Abraham I) - Explicitly set keystone to host mode (Kishon Vijay Abraham I) - Document DT "atu" reg-names requirement for DesignWare core >= 4.80 (Kishon Vijay Abraham I) - Enable dwc iATU unroll for endpoint mode as well as host mode (Kishon Vijay Abraham I) - Add dwc "version" to identify core >= 4.80 for ATU programming (Kishon Vijay Abraham I) - Don't build ARM32-specific keystone code on ARM64 (Kishon Vijay Abraham I) - Add DT binding for keystone PCIe RC in AM654 SoC (Kishon Vijay Abraham I) - Add keystone support for AM654 SoC PCIe RC (Kishon Vijay Abraham I) - Reset keystone PHYs before enabling them (Kishon Vijay Abraham I) - Make of_pci_get_max_link_speed() available to endpoint drivers as well as host drivers (Kishon Vijay Abraham I) - Add keystone support for DT "max-link-speed" property (Kishon Vijay Abraham I) - Add endpoint library support for BAR buffer alignment (Kishon Vijay Abraham I) - Make all dw_pcie_ep_ops structs const (Kishon Vijay Abraham I) - Fix fencepost error in dw_pcie_ep_find_capability() (Kishon Vijay Abraham I) - Add dwc hooks for dbi/dbi2 that share the same address space (Kishon Vijay Abraham I) - Add keystone support for TI AM654x in endpoint mode (Kishon Vijay Abraham I) - Configure designware endpoints to advertise smallest resizable BAR (1MB) (Kishon Vijay Abraham I) - Align designware endpoint ATU windows for raising MSIs (Kishon Vijay Abraham I) - Add endpoint test support for TI AM654x (Kishon Vijay Abraham I) - Fix endpoint test test_reg_bar issue (Kishon Vijay Abraham I) * remotes/lorenzo/pci/keystone: misc: pci_endpoint_test: Fix test_reg_bar to be updated in pci_endpoint_test misc: pci_endpoint_test: Add support to test PCI EP in AM654x PCI: designware-ep: Use aligned ATU window for raising MSI interrupts PCI: designware-ep: Configure Resizable BAR cap to advertise the smallest size PCI: keystone: Add support for PCIe EP in AM654x Platforms dt-bindings: PCI: Add PCI EP DT binding documentation for AM654 PCI: dwc: Add callbacks for accessing dbi2 address space PCI: dwc: Fix dw_pcie_ep_find_capability() to return correct capability offset PCI: dwc: Add const qualifier to struct dw_pcie_ep_ops PCI: endpoint: Add support to specify alignment for buffers allocated to BARs PCI: keystone: Add support to set the max link speed from DT PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers PCI: keystone: Invoke phy_reset() API before enabling PHY PCI: keystone: Add support for PCIe RC in AM654x Platforms dt-bindings: PCI: Add PCI RC DT binding documentation for AM654 PCI: keystone: Prevent ARM32 specific code to be compiled for ARM64 PCI: dwc: Fix ATU identification for designware version >= 4.80 PCI: dwc: Enable iATU unroll for endpoint too dt-bindings: PCI: Document "atu" reg-names PCI: keystone: Explicitly set the PCIe mode dt-bindings: PCI: Add dt-binding to configure PCIe mode PCI: keystone: Move resources initialization to prepare for EP support PCI: keystone: Use platform_get_resource_byname() to get memory resources PCI: keystone: Perform host initialization in a single function dt-bindings: PCI: keystone: Add "reg-names" binding information PCI: keystone: Cleanup error_irq configuration PCI: keystone: Add start_link()/stop_link() dw_pcie_ops PCI: dwc: Remove default MSI initialization for platform specific MSI chips PCI: dwc: Remove Keystone specific dw_pcie_host_ops PCI: keystone: Use Keystone specific msi_irq_chip PCI: dwc: Add support to use non default msi_irq_chip PCI: keystone: Cleanup ks_pcie_msi_irq_handler() PCI: keystone: Use hwirq to get the MSI IRQ number offset PCI: keystone: Add separate functions for configuring MSI and legacy interrupt PCI: keystone: Cleanup interrupt related macros # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h
Diffstat (limited to 'Documentation/devicetree')
-rw-r--r--Documentation/devicetree/bindings/pci/designware-pcie.txt7
-rw-r--r--Documentation/devicetree/bindings/pci/pci-keystone.txt58
2 files changed, 60 insertions, 5 deletions
diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index c124f9bc11f3..5561a1c060d0 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -4,8 +4,11 @@ Required properties:
- compatible:
"snps,dw-pcie" for RC mode;
"snps,dw-pcie-ep" for EP mode;
-- reg: Should contain the configuration address space.
-- reg-names: Must be "config" for the PCIe configuration space.
+- reg: For designware cores version < 4.80 contains the configuration
+ address space. For designware core version >= 4.80, contains
+ the configuration and ATU address space
+- reg-names: Must be "config" for the PCIe configuration space and "atu" for
+ the ATU address space.
(The old way of getting the configuration address space from "ranges"
is deprecated and should be avoided.)
- num-lanes: number of lanes to use
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
index 2030ee0dc4f9..47202a2938f2 100644
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
@@ -11,16 +11,24 @@ described here as well as properties that are not applicable.
Required Properties:-
-compatibility: "ti,keystone-pcie"
-reg: index 1 is the base address and length of DW application registers.
- index 2 is the base address and length of PCI device ID register.
+compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
+ Should be "ti,am654-pcie-rc" for RC on AM654x SoC
+reg: Three register ranges as listed in the reg-names property
+reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
+ TI specific application registers, "config" for the
+ configuration space address
pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
interrupt-cells: should be set to 1
interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
+ (required if the compatible is "ti,keystone-pcie")
+msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
+ (required if the compatible is "ti,am654-pcie-rc".
ti,syscon-pcie-id : phandle to the device control module required to set device
id and vendor id.
+ti,syscon-pcie-mode : phandle to the device control module required to configure
+ PCI in either RC mode or EP mode.
Example:
pcie_msi_intc: msi-interrupt-controller {
@@ -61,3 +69,47 @@ Optional properties:-
DesignWare DT Properties not applicable for Keystone PCI
1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
+
+AM654 PCIe Endpoint
+===================
+
+Required Properties:-
+
+compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
+reg: Four register ranges as listed in the reg-names property
+reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
+ TI specific application registers, "atu" for the
+ Address Translation Unit configuration registers and
+ "addr_space" used to map remote RC address space
+num-ib-windows: As specified in
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
+num-ob-windows: As specified in
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
+num-lanes: As specified in
+ Documentation/devicetree/bindings/pci/designware-pcie.txt
+power-domains: As documented by the generic PM domain bindings in
+ Documentation/devicetree/bindings/power/power_domain.txt.
+ti,syscon-pcie-mode: phandle to the device control module required to configure
+ PCI in either RC mode or EP mode.
+
+Optional properties:-
+
+phys: list of PHY specifiers (used by generic PHY framework)
+phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
+ number of lanes as specified in *num-lanes* property.
+("phys" and "phy-names" DT bindings are specified in
+Documentation/devicetree/bindings/phy/phy-bindings.txt)
+interrupts: platform interrupt for error interrupts.
+
+pcie-ep {
+ compatible = "ti,am654-pcie-ep";
+ reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
+ <0x10000000 0x8000000>, <0x5506000 0x1000>;
+ reg-names = "app", "dbics", "addr_space", "atu";
+ power-domains = <&k3_pds 120>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ num-lanes = <1>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+};