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authorPalmer Dabbelt <palmer@dabbelt.com>2017-06-23 13:31:39 -0700
committerJonathan Corbet <corbet@lwn.net>2017-06-24 08:13:43 -0600
commitf5620df7e395465f4eee6c187a4f956b7100b794 (patch)
treea5b314d139cd904a474aaf4df96bf5e1ce2f847d /Documentation/memory-barriers.txt
parent52b3f239bb692d9b3a68461798fb15c011e4108e (diff)
Documentation: atomic_ops.txt is core-api/atomic_ops.rst
I was reading the memory barries documentation in order to make sure the RISC-V barries were correct, and I found a broken link to the atomic operations documentation. Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com> Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation/memory-barriers.txt')
-rw-r--r--Documentation/memory-barriers.txt10
1 files changed, 5 insertions, 5 deletions
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 732f10ea382e..f1c9eaa45a57 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -498,11 +498,11 @@ And a couple of implicit varieties:
This means that ACQUIRE acts as a minimal "acquire" operation and
RELEASE acts as a minimal "release" operation.
-A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
-and RELEASE variants in addition to fully-ordered and relaxed (no barrier
-semantics) definitions. For compound atomics performing both a load and a
-store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
-only to the store portion of the operation.
+A subset of the atomic operations described in core-api/atomic_ops.rst have
+ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
+barrier semantics) definitions. For compound atomics performing both a load
+and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
+apply only to the store portion of the operation.
Memory barriers are only required where there's a possibility of interaction
between two CPUs or between a CPU and a device. If it can be guaranteed that