diff options
| author | Dave Martin <Dave.Martin@arm.com> | 2019-04-12 13:25:38 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2019-04-18 17:14:02 +0100 |
| commit | 43b8e1f08938c0fd3b8924e846dba89863badc2f (patch) | |
| tree | 7bebb7608f5cc7d5ab05fbeb82bb12592ee86190 /Documentation/virtual | |
| parent | fe365b4ea6c0df3eb44d636c32c5210ae1e58364 (diff) | |
KVM: arm64: Clarify access behaviour for out-of-range SVE register slice IDs
The existing documentation for which SVE register slice IDs are
considered out-of-range, and what happens when userspace tries to
access them, is cryptic.
This patch rewords the text with the aim of making it a bit easier to
understand.
No functional change.
Suggested-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation/virtual')
| -rw-r--r-- | Documentation/virtual/kvm/api.txt | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/Documentation/virtual/kvm/api.txt b/Documentation/virtual/kvm/api.txt index 818ac97fdabc..e410a9f0f0d4 100644 --- a/Documentation/virtual/kvm/api.txt +++ b/Documentation/virtual/kvm/api.txt @@ -2159,8 +2159,9 @@ arm64 SVE registers have the following bit patterns: 0x6050 0000 0015 060 <slice:5> FFR bits[256*slice + 255 : 256*slice] 0x6060 0000 0015 ffff KVM_REG_ARM64_SVE_VLS pseudo-register -Access to slices beyond the maximum vector length configured for the -vcpu (i.e., where 16 * slice >= max_vq (**)) will fail with ENOENT. +Access to register IDs where 2048 * slice >= 128 * max_vq will fail with +ENOENT. max_vq is the vcpu's maximum supported vector length in 128-bit +quadwords: see (**) below. These registers are only accessible on vcpus for which SVE is enabled. See KVM_ARM_VCPU_INIT for details. |