diff options
| author | Mark Brown <broonie@kernel.org> | 2022-07-06 12:06:44 +0100 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2022-07-06 12:06:44 +0100 |
| commit | 945c7683c52ac39e8def05cf826632b52044874a (patch) | |
| tree | 14e6c53755b7b0ddaaa496f3c8e167292d631afe /Documentation | |
| parent | 65b6851d243ff54cbd4adfb887a8af9d04b7f286 (diff) | |
| parent | 6c06ad34eda9e1990313ff80999e1a75a02fa1c0 (diff) | |
Add support of two Audio PLL source
Merge series from Shengjiu Wang <shengjiu.wang@nxp.com>:
i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
The patches implement the functionality to select at runtime
the appropriate AUDIO PLL for root clock, if there is no
two PLL registered, then no action taken.
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/sound/fsl,spdif.yaml | 4 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/sound/fsl-sai.txt | 3 |
2 files changed, 7 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml index f226ec13167a..1d64e8337aa4 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.yaml @@ -58,6 +58,8 @@ properties: slave of the Shared Peripheral Bus and when two or more bus masters (CPU, DMA or DSP) try to access it. This property is optional depending on the SoC design. + - description: PLL clock source for 8kHz series rate, optional. + - description: PLL clock source for 11khz series rate, optional. minItems: 9 clock-names: @@ -72,6 +74,8 @@ properties: - const: rxtx6 - const: rxtx7 - const: spba + - const: pll8k + - const: pll11k minItems: 9 big-endian: diff --git a/Documentation/devicetree/bindings/sound/fsl-sai.txt b/Documentation/devicetree/bindings/sound/fsl-sai.txt index 4c66e6a1a533..fbdefc3fade7 100644 --- a/Documentation/devicetree/bindings/sound/fsl-sai.txt +++ b/Documentation/devicetree/bindings/sound/fsl-sai.txt @@ -21,6 +21,9 @@ Required properties: - clock-names : Must include the "bus" for register access and "mclk1", "mclk2", "mclk3" for bit clock and frame clock providing. + "pll8k", "pll11k" are optional, they are the clock + source for root clock, one is for 8kHz series rates + another one is for 11kHz series rates. - dmas : Generic dma devicetree binding as described in Documentation/devicetree/bindings/dma/dma.txt. |