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authorLinus Torvalds <torvalds@linux-foundation.org>2021-07-03 10:54:08 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2021-07-03 10:54:08 -0700
commita70bb580bfeaead9f685d4c28f7cd685c905d8c3 (patch)
tree273252a458ac5349d6a6190c9b3a748407d060db /Documentation
parent4b820e167bf6f410ace479d8df5b15a574000e75 (diff)
parent6a9a930dc4415b2e8c0bf2085b2b0b2b291053d5 (diff)
Merge tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring: - Refine reserved memory nomap handling - Merge some PCI and non-PCI address handling implementations - Simplify of_address.h header ifdefs - Improve printk handling of some 64-bit types - Convert adi,adv7511, Arm ccree, Arm SCMI, Arm SCU, Arm TWD timer, Arm VIC, arm,sbsa-gwdt, Arm/Amlogic SCPI, Aspeed I2C, Broadcom iProc PWM, linaro,optee-tz, MDIO GPIO, Mediatek RNG, MTD physmap, NXP pcf8563/pcf85263/pcf85363, Renesas TPU, renesas,emev2-smu, renesas,r9a06g032-sysctrl, sysc-rmobile, Tegra20 EMC, TI AM56 PCI, TI OMAP mailbox, TI SCI bindings, virtio-mmio, Zynq FPGA, and ZynqMP RTC to DT schema - Convert mux and mux controller bindings to schema. This includes MDIO IIO, and I2C muxes. - Add Arm PL031 RTC binding schema - Add vendor prefixes for StarFive Technology Co. Ltd. and Insignal Ltd - Fix some stale doc references - Remove stale property-units.txt. Superseded by schema in dt-schema repo. - Fixes for 'unevaluatedProperties' handling (enabled with experimental json-schema support) - Drop redundant usage of minItems and maxItems across the tree - Update some examples to use bindings with a schema * tag 'devicetree-for-5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (83 commits) dt-bindings: Fix 'unevaluatedProperties' errors in DT graph users dt-bindings: display: renesas,du: Fix 'ports' reference dt-bindings: media: adv7180: Add missing video-interfaces.yaml reference dt-bindings: crypto: ccree: Convert to json-schema dt-bindings: fpga: zynq: convert bindings to YAML dt-bindings: rtc: zynqmp: convert bindings to YAML dt-bindings: interrupt-controller: Convert ARM VIC to json-schema of: of_reserved_mem: mark nomap memory instead of removing of: of_reserved_mem: only call memblock_free for normal reserved memory dt-bindings: Drop redundant minItems/maxItems dt-bindings: spmi: Correct 'reg' schema of: reserved-memory: Add stub for RESERVEDMEM_OF_DECLARE() dt-bindings: clk: vc5: Fix example dt-bindings: timer: renesas,tmu: add r8a779a0 TMU support dt-bindings: drm: bridge: adi,adv7511.txt: convert to yaml dt-bindings: PCI: ti,am65: Convert PCIe host/endpoint mode dt-bindings to YAML of: Remove superfluous casts when printing u64 values of: Fix truncation of memory sizes on 32-bit platforms dt-bindings: rtc: nxp,pcf8563: Absorb pcf85263/pcf85363 bindings dt-bindings: pwm: Use examples with documented/matching schema ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/arm/amlogic,scpi.txt27
-rw-r--r--Documentation/devicetree/bindings/arm/arm,scmi.txt239
-rw-r--r--Documentation/devicetree/bindings/arm/arm,scpi.txt219
-rw-r--r--Documentation/devicetree/bindings/arm/arm,scu.yaml46
-rw-r--r--Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt31
-rw-r--r--Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml58
-rw-r--r--Documentation/devicetree/bindings/arm/intel,keembay.yaml2
-rw-r--r--Documentation/devicetree/bindings/arm/juno,scpi.txt26
-rw-r--r--Documentation/devicetree/bindings/arm/keystone/ti,sci.txt86
-rw-r--r--Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml129
-rw-r--r--Documentation/devicetree/bindings/arm/scu.txt28
-rw-r--r--Documentation/devicetree/bindings/arm/ux500/boards.txt4
-rw-r--r--Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml1
-rw-r--r--Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml11
-rw-r--r--Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/idt,versaclock5.yaml7
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml1
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml2
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt98
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml140
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt46
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml62
-rw-r--r--Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml1
-rw-r--r--Documentation/devicetree/bindings/clock/ti,sci-clk.txt36
-rw-r--r--Documentation/devicetree/bindings/clock/ti,sci-clk.yaml49
-rw-r--r--Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml2
-rw-r--r--Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml53
-rw-r--r--Documentation/devicetree/bindings/crypto/arm-cryptocell.txt25
-rw-r--r--Documentation/devicetree/bindings/crypto/fsl-dcp.yaml1
-rw-r--r--Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml6
-rw-r--r--Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml1
-rw-r--r--Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml4
-rw-r--r--Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt143
-rw-r--r--Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml240
-rw-r--r--Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml184
-rw-r--r--Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml3
-rw-r--r--Documentation/devicetree/bindings/display/panel/lvds.yaml46
-rw-r--r--Documentation/devicetree/bindings/display/renesas,du.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/st,stm32-dsi.yaml2
-rw-r--r--Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml1
-rw-r--r--Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml4
-rw-r--r--Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml1
-rw-r--r--Documentation/devicetree/bindings/dma/ti-edma.txt4
-rw-r--r--Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml2
-rw-r--r--Documentation/devicetree/bindings/eeprom/at24.yaml1
-rw-r--r--Documentation/devicetree/bindings/example-schema.yaml2
-rw-r--r--Documentation/devicetree/bindings/firmware/arm,scmi.yaml341
-rw-r--r--Documentation/devicetree/bindings/firmware/arm,scpi.yaml247
-rw-r--r--Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt19
-rw-r--r--Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml52
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-davinci.txt2
-rw-r--r--Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml1
-rw-r--r--Documentation/devicetree/bindings/gpu/vivante,gc.yaml1
-rw-r--r--Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml74
-rw-r--r--Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml1
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-aspeed.txt49
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-davinci.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt2
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt99
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml124
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt74
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml110
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt4
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux.txt73
-rw-r--r--Documentation/devicetree/bindings/i2c/i2c-mux.yaml87
-rw-r--r--Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml2
-rw-r--r--Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml1
-rw-r--r--Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml1
-rw-r--r--Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml2
-rw-r--r--Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt39
-rw-r--r--Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml70
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt41
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml81
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml1
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml1
-rw-r--r--Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml2
-rw-r--r--Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml1
-rw-r--r--Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml1
-rw-r--r--Documentation/devicetree/bindings/mailbox/arm,mhu.yaml48
-rw-r--r--Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml25
-rw-r--r--Documentation/devicetree/bindings/mailbox/omap-mailbox.txt184
-rw-r--r--Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml2
-rw-r--r--Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml308
-rw-r--r--Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/i2c/adv7180.yaml8
-rw-r--r--Documentation/devicetree/bindings/media/i2c/adv7604.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/i2c/imx258.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml23
-rw-r--r--Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml2
-rw-r--r--Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/renesas,drif.yaml1
-rw-r--r--Documentation/devicetree/bindings/media/renesas,vin.yaml3
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml6
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml1
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt130
-rw-r--r--Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml230
-rw-r--r--Documentation/devicetree/bindings/mfd/motorola-cpcap.txt4
-rw-r--r--Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml19
-rw-r--r--Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml2
-rw-r--r--Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml1
-rw-r--r--Documentation/devicetree/bindings/mmc/mtk-sd.yaml2
-rw-r--r--Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml2
-rw-r--r--Documentation/devicetree/bindings/mmc/sdhci-am654.yaml1
-rw-r--r--Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml1
-rw-r--r--Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt4
-rw-r--r--Documentation/devicetree/bindings/mtd/arm-versatile.txt26
-rw-r--r--Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt2
-rw-r--r--Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt13
-rw-r--r--Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt22
-rw-r--r--Documentation/devicetree/bindings/mtd/mtd-physmap.txt114
-rw-r--r--Documentation/devicetree/bindings/mtd/mtd-physmap.yaml208
-rw-r--r--Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt2
-rw-r--r--Documentation/devicetree/bindings/mux/adi,adg792a.txt2
-rw-r--r--Documentation/devicetree/bindings/mux/adi,adgs1408.txt2
-rw-r--r--Documentation/devicetree/bindings/mux/gpio-mux.txt69
-rw-r--r--Documentation/devicetree/bindings/mux/gpio-mux.yaml92
-rw-r--r--Documentation/devicetree/bindings/mux/mux-consumer.yaml46
-rw-r--r--Documentation/devicetree/bindings/mux/mux-controller.txt157
-rw-r--r--Documentation/devicetree/bindings/mux/mux-controller.yaml182
-rw-r--r--Documentation/devicetree/bindings/mux/reg-mux.txt129
-rw-r--r--Documentation/devicetree/bindings/mux/reg-mux.yaml143
-rw-r--r--Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml2
-rw-r--r--Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml2
-rw-r--r--Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt2
-rw-r--r--Documentation/devicetree/bindings/net/can/bosch,m_can.yaml2
-rw-r--r--Documentation/devicetree/bindings/net/can/c_can.txt4
-rw-r--r--Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml2
-rw-r--r--Documentation/devicetree/bindings/net/mdio-gpio.txt27
-rw-r--r--Documentation/devicetree/bindings/net/mdio-gpio.yaml57
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-gpio.txt119
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml135
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt75
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml78
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt82
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml82
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux.txt129
-rw-r--r--Documentation/devicetree/bindings/net/mdio-mux.yaml44
-rw-r--r--Documentation/devicetree/bindings/net/snps,dwmac.yaml2
-rw-r--r--Documentation/devicetree/bindings/net/stm32-dwmac.yaml1
-rw-r--r--Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml2
-rw-r--r--Documentation/devicetree/bindings/pci/loongson.yaml1
-rw-r--r--Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml1
-rw-r--r--Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml2
-rw-r--r--Documentation/devicetree/bindings/pci/pci-keystone.txt115
-rw-r--r--Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml74
-rw-r--r--Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml96
-rw-r--r--Documentation/devicetree/bindings/perf/arm,cmn.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml3
-rw-r--r--Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/mediatek,tphy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml4
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml1
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml2
-rw-r--r--Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml1
-rw-r--r--Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml1
-rw-r--r--Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml1
-rw-r--r--Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt100
-rw-r--r--Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml121
-rw-r--r--Documentation/devicetree/bindings/property-units.txt48
-rw-r--r--Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml1
-rw-r--r--Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt21
-rw-r--r--Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml45
-rw-r--r--Documentation/devicetree/bindings/pwm/pwm.yaml9
-rw-r--r--Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml13
-rw-r--r--Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml26
-rw-r--r--Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml2
-rw-r--r--Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt4
-rw-r--r--Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml3
-rw-r--r--Documentation/devicetree/bindings/reset/fsl,imx-src.yaml1
-rw-r--r--Documentation/devicetree/bindings/reset/ti,sci-reset.txt62
-rw-r--r--Documentation/devicetree/bindings/reset/ti,sci-reset.yaml51
-rw-r--r--Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml1
-rw-r--r--Documentation/devicetree/bindings/rng/mtk-rng.txt22
-rw-r--r--Documentation/devicetree/bindings/rng/mtk-rng.yaml54
-rw-r--r--Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml1
-rw-r--r--Documentation/devicetree/bindings/rtc/arm,pl031.yaml58
-rw-r--r--Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml1
-rw-r--r--Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml58
-rw-r--r--Documentation/devicetree/bindings/rtc/pcf85363.txt17
-rw-r--r--Documentation/devicetree/bindings/rtc/pcf8563.txt29
-rw-r--r--Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml65
-rw-r--r--Documentation/devicetree/bindings/rtc/xlnx-rtc.txt25
-rw-r--r--Documentation/devicetree/bindings/serial/fsl-lpuart.yaml2
-rw-r--r--Documentation/devicetree/bindings/serial/samsung_uart.yaml1
-rw-r--r--Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml1
-rw-r--r--Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt65
-rw-r--r--Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml59
-rw-r--r--Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml1
-rw-r--r--Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml2
-rw-r--r--Documentation/devicetree/bindings/sound/st,stm32-sai.yaml3
-rw-r--r--Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml1
-rw-r--r--Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml2
-rw-r--r--Documentation/devicetree/bindings/spi/spi-davinci.txt2
-rw-r--r--Documentation/devicetree/bindings/spmi/spmi.yaml15
-rw-r--r--Documentation/devicetree/bindings/sram/sram.yaml5
-rw-r--r--Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml2
-rw-r--r--Documentation/devicetree/bindings/thermal/qcom-tsens.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/arm,arch_timer.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml2
-rw-r--r--Documentation/devicetree/bindings/timer/arm,twd-timer.yaml56
-rw-r--r--Documentation/devicetree/bindings/timer/arm,twd.txt53
-rw-r--r--Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/renesas,tmu.yaml1
-rw-r--r--Documentation/devicetree/bindings/timer/renesas,tpu.txt21
-rw-r--r--Documentation/devicetree/bindings/timer/renesas,tpu.yaml56
-rw-r--r--Documentation/devicetree/bindings/usb/cdns,usb3.yaml2
-rw-r--r--Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml2
-rw-r--r--Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml4
-rw-r--r--Documentation/devicetree/bindings/usb/renesas,usbhs.yaml3
-rw-r--r--Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml2
-rw-r--r--Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml2
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.yaml6
-rw-r--r--Documentation/devicetree/bindings/virtio/mmio.txt47
-rw-r--r--Documentation/devicetree/bindings/virtio/mmio.yaml60
-rw-r--r--Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml51
-rw-r--r--Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml50
-rw-r--r--Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt31
-rw-r--r--Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml1
-rw-r--r--Documentation/devicetree/bindings/writing-bindings.rst3
239 files changed, 4933 insertions, 3620 deletions
diff --git a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt b/Documentation/devicetree/bindings/arm/amlogic,scpi.txt
deleted file mode 100644
index 5ab59da052df..000000000000
--- a/Documentation/devicetree/bindings/arm/amlogic,scpi.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-(in addition to the standard binding in [0])
-----------------------------------------------------------
-Required properties
-
-- compatible : should be "amlogic,meson-gxbb-scpi"
-
-AMLOGIC SRAM and Shared Memory for SCPI
-------------------------------------
-
-Required properties:
-- compatible : should be "amlogic,meson-gxbb-sram"
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- compatible : should be "amlogic,meson-gxbb-scp-shmem" for SRAM based shared
- memory on Amlogic GXBB SoC.
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-SCPI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- compatible : should be "amlogic,meson-gxbb-scpi-sensors".
-
-[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
diff --git a/Documentation/devicetree/bindings/arm/arm,scmi.txt b/Documentation/devicetree/bindings/arm/arm,scmi.txt
deleted file mode 100644
index 667d58e0a659..000000000000
--- a/Documentation/devicetree/bindings/arm/arm,scmi.txt
+++ /dev/null
@@ -1,239 +0,0 @@
-System Control and Management Interface (SCMI) Message Protocol
-----------------------------------------------------------
-
-The SCMI is intended to allow agents such as OSPM to manage various functions
-that are provided by the hardware platform it is running on, including power
-and performance functions.
-
-This binding is intended to define the interface the firmware implementing
-the SCMI as described in ARM document number ARM DEN 0056A ("ARM System Control
-and Management Interface Platform Design Document")[0] provide for OSPM in
-the device tree.
-
-Required properties:
-
-The scmi node with the following properties shall be under the /firmware/ node.
-
-- compatible : shall be "arm,scmi" or "arm,scmi-smc" for smc/hvc transports
-- mboxes: List of phandle and mailbox channel specifiers. It should contain
- exactly one or two mailboxes, one for transmitting messages("tx")
- and another optional for receiving the notifications("rx") if
- supported.
-- shmem : List of phandle pointing to the shared memory(SHM) area as per
- generic mailbox client binding.
-- #address-cells : should be '1' if the device has sub-nodes, maps to
- protocol identifier for a given sub-node.
-- #size-cells : should be '0' as 'reg' property doesn't have any size
- associated with it.
-- arm,smc-id : SMC id required when using smc or hvc transports
-
-Optional properties:
-
-- mbox-names: shall be "tx" or "rx" depending on mboxes entries.
-
-- interrupts : when using smc or hvc transports, this optional
- property indicates that msg completion by the platform is indicated
- by an interrupt rather than by the return of the smc call. This
- should not be used except when the platform requires such behavior.
-
-- interrupt-names : if "interrupts" is present, interrupt-names must also
- be present and have the value "a2p".
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
-about the generic mailbox controller and client driver bindings.
-
-The mailbox is the only permitted method of calling the SCMI firmware.
-Mailbox doorbell is used as a mechanism to alert the presence of a
-messages and/or notification.
-
-Each protocol supported shall have a sub-node with corresponding compatible
-as described in the following sections. If the platform supports dedicated
-communication channel for a particular protocol, the 3 properties namely:
-mboxes, mbox-names and shmem shall be present in the sub-node corresponding
-to that protocol.
-
-Clock/Performance bindings for the clocks/OPPs based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Required properties:
-- #clock-cells : Should be 1. Contains the Clock ID value used by SCMI commands.
-
-Power domain bindings for the power domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI power domain providers uses the generic power
-domain binding[2].
-
-Required properties:
- - #power-domain-cells : Should be 1. Contains the device or the power
- domain ID value used by SCMI commands.
-
-Regulator bindings for the SCMI Regulator based on SCMI Message Protocol
-------------------------------------------------------------
-An SCMI Regulator is permanently bound to a well defined SCMI Voltage Domain,
-and should be always positioned as a root regulator.
-It does not support any current operation.
-
-SCMI Regulators are grouped under a 'regulators' node which in turn is a child
-of the SCMI Voltage protocol node inside the desired SCMI instance node.
-
-This binding uses the common regulator binding[6].
-
-Required properties:
- - reg : shall identify an existent SCMI Voltage Domain.
-
-Sensor bindings for the sensors based on SCMI Message Protocol
---------------------------------------------------------------
-SCMI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- #thermal-sensor-cells: should be set to 1. This property follows the
- thermal device tree bindings[3].
-
- Valid cell values are raw identifiers (Sensor ID)
- as used by the firmware. Refer to platform details
- for your implementation for the IDs to use.
-
-Reset signal bindings for the reset domains based on SCMI Message Protocol
-------------------------------------------------------------
-
-This binding for the SCMI reset domain providers uses the generic reset
-signal binding[5].
-
-Required properties:
- - #reset-cells : Should be 1. Contains the reset domain ID value used
- by SCMI commands.
-
-SRAM and Shared Memory for SCMI
--------------------------------
-
-A small area of SRAM is reserved for SCMI communication between application
-processors and SCP.
-
-The properties should follow the generic mmio-sram description found in [4]
-
-Each sub-node represents the reserved area for SCMI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,scmi-shmem" for Non-secure SRAM based
- shared memory
-
-[0] http://infocenter.arm.com/help/topic/com.arm.doc.den0056a/index.html
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/power/power-domain.yaml
-[3] Documentation/devicetree/bindings/thermal/thermal*.yaml
-[4] Documentation/devicetree/bindings/sram/sram.yaml
-[5] Documentation/devicetree/bindings/reset/reset.txt
-[6] Documentation/devicetree/bindings/regulator/regulator.yaml
-
-Example:
-
-sram@50000000 {
- compatible = "mmio-sram";
- reg = <0x0 0x50000000 0x0 0x10000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x50000000 0x10000>;
-
- cpu_scp_lpri: scp-shmem@0 {
- compatible = "arm,scmi-shmem";
- reg = <0x0 0x200>;
- };
-
- cpu_scp_hpri: scp-shmem@200 {
- compatible = "arm,scmi-shmem";
- reg = <0x200 0x200>;
- };
-};
-
-mailbox@40000000 {
- ....
- #mbox-cells = <1>;
- reg = <0x0 0x40000000 0x0 0x10000>;
-};
-
-firmware {
-
- ...
-
- scmi {
- compatible = "arm,scmi";
- mboxes = <&mailbox 0 &mailbox 1>;
- mbox-names = "tx", "rx";
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- scmi_devpd: protocol@11 {
- reg = <0x11>;
- #power-domain-cells = <1>;
- };
-
- scmi_dvfs: protocol@13 {
- reg = <0x13>;
- #clock-cells = <1>;
- };
-
- scmi_clk: protocol@14 {
- reg = <0x14>;
- #clock-cells = <1>;
- };
-
- scmi_sensors0: protocol@15 {
- reg = <0x15>;
- #thermal-sensor-cells = <1>;
- };
-
- scmi_reset: protocol@16 {
- reg = <0x16>;
- #reset-cells = <1>;
- };
-
- scmi_voltage: protocol@17 {
- reg = <0x17>;
-
- regulators {
- regulator_devX: regulator@0 {
- reg = <0x0>;
- regulator-max-microvolt = <3300000>;
- };
-
- regulator_devY: regulator@9 {
- reg = <0x9>;
- regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <4200000>;
- };
-
- ...
- };
- };
- };
-};
-
-cpu@0 {
- ...
- reg = <0 0>;
- clocks = <&scmi_dvfs 0>;
-};
-
-hdlcd@7ff60000 {
- ...
- reg = <0 0x7ff60000 0 0x1000>;
- clocks = <&scmi_clk 4>;
- power-domains = <&scmi_devpd 1>;
- resets = <&scmi_reset 10>;
-};
-
-thermal-zones {
- soc_thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
- /* sensor ID */
- thermal-sensors = <&scmi_sensors0 3>;
- ...
- };
-};
diff --git a/Documentation/devicetree/bindings/arm/arm,scpi.txt b/Documentation/devicetree/bindings/arm/arm,scpi.txt
deleted file mode 100644
index bcd6c3ec471e..000000000000
--- a/Documentation/devicetree/bindings/arm/arm,scpi.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-----------------------------------------------------------
-
-Firmware implementing the SCPI described in ARM document number ARM DUI 0922B
-("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be used
-by Linux to initiate various system control and power operations.
-
-Required properties:
-
-- compatible : should be
- * "arm,scpi" : For implementations complying to SCPI v1.0 or above
- * "arm,scpi-pre-1.0" : For implementations complying to all
- unversioned releases prior to SCPI v1.0
-- mboxes: List of phandle and mailbox channel specifiers
- All the channels reserved by remote SCP firmware for use by
- SCPI message protocol should be specified in any order
-- shmem : List of phandle pointing to the shared memory(SHM) area between the
- processors using these mailboxes for IPC, one for each mailbox
- SHM can be any memory reserved for the purpose of this communication
- between the processors.
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt
-for more details about the generic mailbox controller and
-client driver bindings.
-
-Clock bindings for the clocks based on SCPI Message Protocol
-------------------------------------------------------------
-
-This binding uses the common clock binding[1].
-
-Container Node
-==============
-Required properties:
-- compatible : should be "arm,scpi-clocks"
- All the clocks provided by SCP firmware via SCPI message
- protocol much be listed as sub-nodes under this node.
-
-Sub-nodes
-=========
-Required properties:
-- compatible : shall include one of the following
- "arm,scpi-dvfs-clocks" - all the clocks that are variable and index based.
- These clocks don't provide an entire range of values between the
- limits but only discrete points within the range. The firmware
- provides the mapping for each such operating frequency and the
- index associated with it. The firmware also manages the
- voltage scaling appropriately with the clock scaling.
- "arm,scpi-variable-clocks" - all the clocks that are variable and provide full
- range within the specified range. The firmware provides the
- range of values within a specified range.
-
-Other required properties for all clocks(all from common clock binding):
-- #clock-cells : Should be 1. Contains the Clock ID value used by SCPI commands.
-- clock-output-names : shall be the corresponding names of the outputs.
-- clock-indices: The identifying number for the clocks(i.e.clock_id) in the
- node. It can be non linear and hence provide the mapping of identifiers
- into the clock-output-names array.
-
-SRAM and Shared Memory for SCPI
--------------------------------
-
-A small area of SRAM is reserved for SCPI communication between application
-processors and SCP.
-
-The properties should follow the generic mmio-sram description found in [3]
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,scp-shmem" for Non-secure SRAM based
- shared memory
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-SCPI provides an API to access the various sensors on the SoC.
-
-Required properties:
-- compatible : should be "arm,scpi-sensors".
-- #thermal-sensor-cells: should be set to 1. This property follows the
- thermal device tree bindings[2].
-
- Valid cell values are raw identifiers (Sensor ID)
- as used by the firmware. Refer to platform details
- for your implementation for the IDs to use.
-
-Power domain bindings for the power domains based on SCPI Message Protocol
-------------------------------------------------------------
-
-This binding uses the generic power domain binding[4].
-
-PM domain providers
-===================
-
-Required properties:
- - #power-domain-cells : Should be 1. Contains the device or the power
- domain ID value used by SCPI commands.
- - num-domains: Total number of power domains provided by SCPI. This is
- needed as the SCPI message protocol lacks a mechanism to
- query this information at runtime.
-
-PM domain consumers
-===================
-
-Required properties:
- - power-domains : A phandle and PM domain specifier as defined by bindings of
- the power controller specified by phandle.
-
-[0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/thermal/thermal*.yaml
-[3] Documentation/devicetree/bindings/sram/sram.yaml
-[4] Documentation/devicetree/bindings/power/power-domain.yaml
-
-Example:
-
-sram: sram@50000000 {
- compatible = "arm,juno-sram-ns", "mmio-sram";
- reg = <0x0 0x50000000 0x0 0x10000>;
-
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x0 0x50000000 0x10000>;
-
- cpu_scp_lpri: scp-shmem@0 {
- compatible = "arm,juno-scp-shmem";
- reg = <0x0 0x200>;
- };
-
- cpu_scp_hpri: scp-shmem@200 {
- compatible = "arm,juno-scp-shmem";
- reg = <0x200 0x200>;
- };
-};
-
-mailbox: mailbox0@40000000 {
- ....
- #mbox-cells = <1>;
-};
-
-scpi_protocol: scpi@2e000000 {
- compatible = "arm,scpi";
- mboxes = <&mailbox 0 &mailbox 1>;
- shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
-
- clocks {
- compatible = "arm,scpi-clocks";
-
- scpi_dvfs: scpi_clocks@0 {
- compatible = "arm,scpi-dvfs-clocks";
- #clock-cells = <1>;
- clock-indices = <0>, <1>, <2>;
- clock-output-names = "atlclk", "aplclk","gpuclk";
- };
- scpi_clk: scpi_clocks@3 {
- compatible = "arm,scpi-variable-clocks";
- #clock-cells = <1>;
- clock-indices = <3>, <4>;
- clock-output-names = "pxlclk0", "pxlclk1";
- };
- };
-
- scpi_sensors0: sensors {
- compatible = "arm,scpi-sensors";
- #thermal-sensor-cells = <1>;
- };
-
- scpi_devpd: scpi-power-domains {
- compatible = "arm,scpi-power-domains";
- num-domains = <2>;
- #power-domain-cells = <1>;
- };
-};
-
-cpu@0 {
- ...
- reg = <0 0>;
- clocks = <&scpi_dvfs 0>;
-};
-
-hdlcd@7ff60000 {
- ...
- reg = <0 0x7ff60000 0 0x1000>;
- clocks = <&scpi_clk 4>;
- power-domains = <&scpi_devpd 1>;
-};
-
-thermal-zones {
- soc_thermal {
- polling-delay-passive = <100>;
- polling-delay = <1000>;
-
- /* sensor ID */
- thermal-sensors = <&scpi_sensors0 3>;
- ...
- };
-};
-
-In the above example, the #clock-cells is set to 1 as required.
-scpi_dvfs has 3 output clocks namely: atlclk, aplclk, and gpuclk with 0,
-1 and 2 as clock-indices. scpi_clk has 2 output clocks namely: pxlclk0
-and pxlclk1 with 3 and 4 as clock-indices.
-
-The first consumer in the example is cpu@0 and it has '0' as the clock
-specifier which points to the first entry in the output clocks of
-scpi_dvfs i.e. "atlclk".
-
-Similarly the second example is hdlcd@7ff60000 and it has pxlclk1 as input
-clock. '4' in the clock specifier here points to the second entry
-in the output clocks of scpi_clocks i.e. "pxlclk1"
-
-The thermal-sensors property in the soc_thermal node uses the
-temperature sensor provided by SCP firmware to setup a thermal
-zone. The ID "3" is the sensor identifier for the temperature sensor
-as used by the firmware.
-
-The num-domains property in scpi-power-domains domain specifies that
-SCPI provides 2 power domains. The hdlcd node uses the power domain with
-domain ID 1.
diff --git a/Documentation/devicetree/bindings/arm/arm,scu.yaml b/Documentation/devicetree/bindings/arm/arm,scu.yaml
new file mode 100644
index 000000000000..dae2aa27e641
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,scu.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,scu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Snoop Control Unit (SCU)
+
+maintainers:
+ - Linus Walleij <linus.walleij@linaro.org>
+
+description: |
+ As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
+ with a Snoop Control Unit. The register range is usually 256 (0x100)
+ bytes.
+
+ References:
+ - Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
+ Revision r2p0
+ - Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
+ Revision r0p1
+ - ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
+ Manial Revision r2p0
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-scu
+ - arm,cortex-a5-scu
+ - arm,arm11mp-scu
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ scu@a0410000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xa0410000 0x100>;
+ };
diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt
deleted file mode 100644
index d38834c67dff..000000000000
--- a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-OP-TEE Device Tree Bindings
-
-OP-TEE is a piece of software using hardware features to provide a Trusted
-Execution Environment. The security can be provided with ARM TrustZone, but
-also by virtualization or a separate chip.
-
-We're using "linaro" as the first part of the compatible property for
-the reference implementation maintained by Linaro.
-
-* OP-TEE based on ARM TrustZone required properties:
-
-- compatible : should contain "linaro,optee-tz"
-
-- method : The method of calling the OP-TEE Trusted OS. Permitted
- values are:
-
- "smc" : SMC #0, with the register assignments specified
- in drivers/tee/optee/optee_smc.h
-
- "hvc" : HVC #0, with the register assignments specified
- in drivers/tee/optee/optee_smc.h
-
-
-
-Example:
- firmware {
- optee {
- compatible = "linaro,optee-tz";
- method = "smc";
- };
- };
diff --git a/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
new file mode 100644
index 000000000000..c24047c1fdd5
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/firmware/linaro,optee-tz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OP-TEE Device Tree Bindings
+
+maintainers:
+ - Jens Wiklander <jens.wiklander@linaro.org>
+
+description: |
+ OP-TEE is a piece of software using hardware features to provide a Trusted
+ Execution Environment. The security can be provided with ARM TrustZone, but
+ also by virtualization or a separate chip.
+
+ We're using "linaro" as the first part of the compatible property for
+ the reference implementation maintained by Linaro.
+
+properties:
+ $nodename:
+ const: optee
+
+ compatible:
+ const: linaro,optee-tz
+
+ method:
+ enum: [smc, hvc]
+ description: |
+ The method of calling the OP-TEE Trusted OS depending on smc or hvc
+ instruction usage.
+ SMC #0, register assignments
+ or
+ HVC #0, register assignments
+ register assignments are specified in drivers/tee/optee/optee_smc.h
+
+required:
+ - compatible
+ - method
+
+additionalProperties: false
+
+examples:
+ - |
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+ };
+
+ - |
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "hvc";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/intel,keembay.yaml b/Documentation/devicetree/bindings/arm/intel,keembay.yaml
index 69cd30872928..107e686ab207 100644
--- a/Documentation/devicetree/bindings/arm/intel,keembay.yaml
+++ b/Documentation/devicetree/bindings/arm/intel,keembay.yaml
@@ -11,6 +11,8 @@ maintainers:
- Daniele Alessandrelli <daniele.alessandrelli@intel.com>
properties:
+ $nodename:
+ const: '/'
compatible:
items:
- enum:
diff --git a/Documentation/devicetree/bindings/arm/juno,scpi.txt b/Documentation/devicetree/bindings/arm/juno,scpi.txt
deleted file mode 100644
index 2ace8696bbee..000000000000
--- a/Documentation/devicetree/bindings/arm/juno,scpi.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-System Control and Power Interface (SCPI) Message Protocol
-(in addition to the standard binding in [0])
-
-Juno SRAM and Shared Memory for SCPI
-------------------------------------
-
-Required properties:
-- compatible : should be "arm,juno-sram-ns" for Non-secure SRAM
-
-Each sub-node represents the reserved area for SCPI.
-
-Required sub-node properties:
-- reg : The base offset and size of the reserved area with the SRAM
-- compatible : should be "arm,juno-scp-shmem" for Non-secure SRAM based
- shared memory on Juno platforms
-
-Sensor bindings for the sensors based on SCPI Message Protocol
---------------------------------------------------------------
-Required properties:
-- compatible : should be "arm,scpi-sensors".
-- #thermal-sensor-cells: should be set to 1.
- For Juno R0 and Juno R1 refer to [1] for the
- sensor identifiers
-
-[0] Documentation/devicetree/bindings/arm/arm,scpi.txt
-[1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0922b/apas03s22.html
diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt b/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
deleted file mode 100644
index 6f0cd31c1520..000000000000
--- a/Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
+++ /dev/null
@@ -1,86 +0,0 @@
-Texas Instruments System Control Interface (TI-SCI) Message Protocol
---------------------------------------------------------------------
-
-Texas Instrument's processors including those belonging to Keystone generation
-of processors have separate hardware entity which is now responsible for the
-management of the System on Chip (SoC) system. These include various system
-level functions as well.
-
-An example of such an SoC is K2G, which contains the system control hardware
-block called Power Management Micro Controller (PMMC). This hardware block is
-initialized early into boot process and provides services to Operating Systems
-on multiple processors including ones running Linux.
-
-See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
-
-TI-SCI controller Device Node:
-=============================
-
-The TI-SCI node describes the Texas Instrument's System Controller entity node.
-This parent node may optionally have additional children nodes which describe
-specific functionality such as clocks, power domain, reset or additional
-functionality as may be required for the SoC. This hierarchy also describes the
-relationship between the TI-SCI parent node to the child node.
-
-Required properties:
--------------------
-- compatible: should be "ti,k2g-sci" for TI 66AK2G SoC
- should be "ti,am654-sci" for for TI AM654 SoC
-- mbox-names:
- "rx" - Mailbox corresponding to receive path
- "tx" - Mailbox corresponding to transmit path
-
-- mboxes: Mailboxes corresponding to the mbox-names. Each value of the mboxes
- property should contain a phandle to the mailbox controller device
- node and an args specifier that will be the phandle to the intended
- sub-mailbox child node to be used for communication.
-
-See Documentation/devicetree/bindings/mailbox/mailbox.txt for more details
-about the generic mailbox controller and client driver bindings. Also see
-Documentation/devicetree/bindings/mailbox/ti,message-manager.txt for typical
-controller that is used to communicate with this System controllers.
-
-Optional Properties:
--------------------
-- reg-names:
- debug_messages - Map the Debug message region
-- reg: register space corresponding to the debug_messages
-- ti,system-reboot-controller: If system reboot can be triggered by SoC reboot
-- ti,host-id: Integer value corresponding to the host ID assigned by Firmware
- for identification of host processing entities such as virtual
- machines
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ti,host-id = <2>;
- mbox-names = "rx", "tx";
- mboxes= <&msgmgr &msgmgr_proxy_pmmc_rx>,
- <&msgmgr &msgmgr_proxy_pmmc_tx>;
- reg-names = "debug_messages";
- reg = <0x02921800 0x800>;
- };
-
-
-TI-SCI Client Device Node:
-=========================
-
-Client nodes are maintained as children of the relevant TI-SCI device node.
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ...
-
- my_clk_node: clk_node {
- ...
- ...
- };
-
- my_pd_node: pd_node {
- ...
- ...
- };
- };
diff --git a/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
new file mode 100644
index 000000000000..34f5f877d444
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
@@ -0,0 +1,129 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/keystone/ti,sci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI controller device node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Texas Instrument's processors including those belonging to Keystone generation
+ of processors have separate hardware entity which is now responsible for the
+ management of the System on Chip (SoC) system. These include various system
+ level functions as well.
+
+ An example of such an SoC is K2G, which contains the system control hardware
+ block called Power Management Micro Controller (PMMC). This hardware block is
+ initialized early into boot process and provides services to Operating Systems
+ on multiple processors including ones running Linux.
+
+ See http://processors.wiki.ti.com/index.php/TISCI for protocol definition.
+
+ The TI-SCI node describes the Texas Instrument's System Controller entity node.
+ This parent node may optionally have additional children nodes which describe
+ specific functionality such as clocks, power domain, reset or additional
+ functionality as may be required for the SoC. This hierarchy also describes the
+ relationship between the TI-SCI parent node to the child node.
+
+properties:
+ $nodename:
+ pattern: "^system-controller@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - description: System controller on TI 66AK2G SoC and other K3 SoCs
+ items:
+ - const: ti,k2g-sci
+ - description: System controller on TI AM654 SoC
+ items:
+ - const: ti,am654-sci
+
+ reg-names:
+ description: |
+ Specifies the debug messages memory mapped region that is optionally
+ made available from TI-SCI controller.
+ const: debug_messages
+
+ reg:
+ minItems: 1
+
+ mbox-names:
+ description: |
+ Specifies the mailboxes used to communicate with TI-SCI Controller
+ made available from TI-SCI controller.
+ items:
+ - const: rx
+ - const: tx
+
+ mboxes:
+ minItems: 2
+
+ ti,system-reboot-controller:
+ description: Determines If system reboot can be triggered by SoC reboot
+ type: boolean
+
+ ti,host-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: |
+ Value corresponding to the host ID assigned by Firmware
+ for identification of host processing entities such as virtual machines.
+
+ power-controller:
+ type: object
+ $ref: /schemas/soc/ti/sci-pm-domain.yaml#
+
+ clock-controller:
+ type: object
+ $ref: /schemas/clock/ti,sci-clk.yaml#
+
+ reset-controller:
+ type: object
+ $ref: /schemas/reset/ti,sci-reset.yaml#
+
+required:
+ - compatible
+ - mbox-names
+ - mboxes
+
+additionalProperties: false
+
+examples:
+ - |
+ pmmc: system-controller@2921800 {
+ compatible = "ti,k2g-sci";
+ ti,system-reboot-controller;
+ mbox-names = "rx", "tx";
+ mboxes= <&msgmgr 5 2>,
+ <&msgmgr 0 0>;
+ reg-names = "debug_messages";
+ reg = <0x02921800 0x800>;
+ };
+
+ - |
+ dmsc: system-controller@44083000 {
+ compatible = "ti,k2g-sci";
+ ti,host-id = <12>;
+ mbox-names = "rx", "tx";
+ mboxes= <&secure_proxy_main 11>,
+ <&secure_proxy_main 13>;
+ reg-names = "debug_messages";
+ reg = <0x44083000 0x1000>;
+
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
+
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
+
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/arm/scu.txt b/Documentation/devicetree/bindings/arm/scu.txt
deleted file mode 100644
index 74d0a780ce51..000000000000
--- a/Documentation/devicetree/bindings/arm/scu.txt
+++ /dev/null
@@ -1,28 +0,0 @@
-* ARM Snoop Control Unit (SCU)
-
-As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
-with a Snoop Control Unit. The register range is usually 256 (0x100)
-bytes.
-
-References:
-
-- Cortex-A9: see DDI0407E Cortex-A9 MPCore Technical Reference Manual
- Revision r2p0
-- Cortex-A5: see DDI0434B Cortex-A5 MPCore Technical Reference Manual
- Revision r0p1
-- ARM11 MPCore: see DDI0360F ARM 11 MPCore Processor Technical Reference
- Manial Revision r2p0
-
-- compatible : Should be:
- "arm,cortex-a9-scu"
- "arm,cortex-a5-scu"
- "arm,arm11mp-scu"
-
-- reg : Specify the base address and the size of the SCU register window.
-
-Example:
-
-scu@a0410000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0xa0410000 0x100>;
-};
diff --git a/Documentation/devicetree/bindings/arm/ux500/boards.txt b/Documentation/devicetree/bindings/arm/ux500/boards.txt
index 89408de55bfd..18d55532d31e 100644
--- a/Documentation/devicetree/bindings/arm/ux500/boards.txt
+++ b/Documentation/devicetree/bindings/arm/ux500/boards.txt
@@ -20,13 +20,13 @@ during retention, system won't boot without this):
compatible = "ste,dbx500-backupram"
scu:
- see binding for arm/scu.txt
+ see binding for arm/arm,scu.yaml
interrupt-controller:
see binding for interrupt-controller/arm,gic.txt
timer:
- see binding for timer/arm,twd.txt
+ see binding for timer/arm,twd-timer.yaml
clocks:
see binding for clocks/ux500.txt
diff --git a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
index a75e9a8f539a..3c7a2425f3e6 100644
--- a/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
+++ b/Documentation/devicetree/bindings/ata/nvidia,tegra-ahci.yaml
@@ -20,7 +20,6 @@ properties:
reg:
minItems: 2
- maxItems: 3
items:
- description: AHCI registers
- description: SATA configuration and IPFS registers
diff --git a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
index d06096a7ba4b..c060c7914cae 100644
--- a/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
+++ b/Documentation/devicetree/bindings/ata/renesas,rcar-sata.yaml
@@ -53,6 +53,17 @@ required:
- reg
- interrupts
- clocks
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ const: renesas,sata-r8a7779
+then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
index a27025cd3909..c4b7243ddcf2 100644
--- a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
@@ -51,7 +51,6 @@ properties:
clocks:
minItems: 2
- maxItems: 4
items:
- description: High Frequency Oscillator (usually at 24MHz)
- description: Low Frequency Oscillator (usually at 32kHz)
@@ -60,7 +59,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 4
items:
- const: hosc
- const: losc
diff --git a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
index 28675b0b80f1..26ed040bc717 100644
--- a/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
+++ b/Documentation/devicetree/bindings/clock/idt,versaclock5.yaml
@@ -84,6 +84,7 @@ patternProperties:
idt,slew-percent:
description: The Slew rate control for CMOS single-ended.
enum: [ 80, 85, 90, 100 ]
+ additionalProperties: false
required:
- compatible
@@ -139,13 +140,13 @@ examples:
clock-names = "xin";
OUT1 {
- idt,drive-mode = <VC5_CMOSD>;
- idt,voltage-microvolts = <1800000>;
+ idt,mode = <VC5_CMOSD>;
+ idt,voltage-microvolt = <1800000>;
idt,slew-percent = <80>;
};
OUT4 {
- idt,drive-mode = <VC5_LVDS>;
+ idt,mode = <VC5_LVDS>;
};
};
};
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
index eacccc88bbf6..8e2eac6cbfb9 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
@@ -46,7 +46,6 @@ properties:
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- const: calib_backup
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
index 1121b3934cb9..b0d1c65aa354 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sdx55.yaml
@@ -27,7 +27,6 @@ properties:
- description: Sleep clock source
- description: PLL test clock source (Optional clock)
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -35,7 +34,6 @@ properties:
- const: sleep_clk
- const: core_bi_pll_test_se # Optional clock
minItems: 2
- maxItems: 3
'#clock-cells':
const: 1
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
index 78f35832aa41..1122700dcc2b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8350.yaml
@@ -36,7 +36,6 @@ properties:
- description: USB3 phy wrapper pipe clock source (Optional clock)
- description: USB3 phy sec pipe clock source (Optional clock)
minItems: 2
- maxItems: 13
clock-names:
items:
@@ -54,7 +53,6 @@ properties:
- const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock
- const: usb3_uni_phy_sec_gcc_usb30_pipe_clk # Optional clock
minItems: 2
- maxItems: 13
'#clock-cells':
const: 1
diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
deleted file mode 100644
index 268ca615459e..000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Device tree Clock bindings for Renesas EMMA Mobile EV2
-
-This binding uses the common clock binding.
-
-* SMU
-System Management Unit described in user's manual R19UH0037EJ1000_SMU.
-This is not a clock provider, but clocks under SMU depend on it.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu"
-- reg: Address and Size of SMU registers
-
-* SMU_CLKDIV
-Function block with an input mux and a divider, which corresponds to
-"Serial clock generator" in fig."Clock System Overview" of the manual,
-and "xxx frequency division setting register" (XXXCLKDIV) registers.
-This makes internal (neither input nor output) clock that is provided
-to input of xxxGCLK block.
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-clkdiv"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Parent clocks. Input clocks as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-* SMU_GCLK
-Clock gating node shown as "Clock stop processing block" in the
-fig."Clock System Overview" of the manual.
-Registers are "xxx clock gate control register" (XXXGCLKCTRL).
-
-Required properties:
-- compatible: Should be "renesas,emev2-smu-gclk"
-- reg: Byte offset from SMU base and Bit position in the register
-- clocks: Input clock as described in clock-bindings.txt
-- #clock-cells: Should be <0>
-
-Example of provider:
-
-usia_u0_sclkdiv: usia_u0_sclkdiv {
- compatible = "renesas,emev2-smu-clkdiv";
- reg = <0x610 0>;
- clocks = <&pll3_fo>, <&pll4_fo>, <&pll1_fo>, <&osc1_fo>;
- #clock-cells = <0>;
-};
-
-usia_u0_sclk: usia_u0_sclk {
- compatible = "renesas,emev2-smu-gclk";
- reg = <0x4a0 1>;
- clocks = <&usia_u0_sclkdiv>;
- #clock-cells = <0>;
-};
-
-Example of consumer:
-
-serial@e1020000 {
- compatible = "renesas,em-uart";
- reg = <0xe1020000 0x38>;
- interrupts = <0 8 0>;
- clocks = <&usia_u0_sclk>;
- clock-names = "sclk";
-};
-
-Example of clock-tree description:
-
- This describes a clock path in the clock tree
- c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
-
-smu@e0110000 {
- compatible = "renesas,emev2-smu";
- reg = <0xe0110000 0x10000>;
- #address-cells = <2>;
- #size-cells = <0>;
-
- c32ki: c32ki {
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- #clock-cells = <0>;
- };
- pll3_fo: pll3_fo {
- compatible = "fixed-factor-clock";
- clocks = <&c32ki>;
- clock-div = <1>;
- clock-mult = <7000>;
- #clock-cells = <0>;
- };
- usia_u0_sclkdiv: usia_u0_sclkdiv {
- compatible = "renesas,emev2-smu-clkdiv";
- reg = <0x610 0>;
- clocks = <&pll3_fo>;
- #clock-cells = <0>;
- };
- usia_u0_sclk: usia_u0_sclk {
- compatible = "renesas,emev2-smu-gclk";
- reg = <0x4a0 1>;
- clocks = <&usia_u0_sclkdiv>;
- #clock-cells = <0>;
- };
-};
diff --git a/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
new file mode 100644
index 000000000000..4d9a64800481
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,emev2-smu.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,emev2-smu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas EMMA Mobile EV2 System Management Unit
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The System Management Unit is described in user's manual R19UH0037EJ1000_SMU.
+ This is not a clock provider, but clocks under SMU depend on it.
+
+properties:
+ compatible:
+ const: renesas,emev2-smu
+
+ reg:
+ maxItems: 1
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+patternProperties:
+ ".*sclkdiv@.*":
+ type: object
+
+ description: |
+ Function block with an input mux and a divider, which corresponds to
+ "Serial clock generator" in fig. "Clock System Overview" of the manual,
+ and "xxx frequency division setting register" (XXXCLKDIV) registers.
+ This makes internal (neither input nor output) clock that is provided
+ to input of xxxGCLK block.
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-clkdiv
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+ ".*sclk@.*":
+ type: object
+
+ description: |
+ Clock gating node shown as "Clock stop processing block" in the
+ fig. "Clock System Overview" of the manual.
+ Registers are "xxx clock gate control register" (XXXGCLKCTRL).
+
+ properties:
+ compatible:
+ const: renesas,emev2-smu-gclk
+
+ reg:
+ maxItems: 1
+ description:
+ Byte offset from SMU base and Bit position in the register.
+
+ clocks:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+ additionalProperties: false
+
+additionalProperties: true
+
+examples:
+ - |
+ // Example of clock-tree description:
+ //
+ // This describes a clock path in the clock tree
+ // c32ki -> pll3_fo -> usia_u0_sclkdiv -> usia_u0_sclk
+ clocks@e0110000 {
+ compatible = "renesas,emev2-smu";
+ reg = <0xe0110000 0x10000>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ c32ki: c32ki {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+ pll3_fo: pll3_fo {
+ compatible = "fixed-factor-clock";
+ clocks = <&c32ki>;
+ clock-div = <1>;
+ clock-mult = <7000>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclkdiv: usia_u0_sclkdiv@610,0 {
+ compatible = "renesas,emev2-smu-clkdiv";
+ reg = <0x610 0>;
+ clocks = <&pll3_fo>;
+ #clock-cells = <0>;
+ };
+ usia_u0_sclk: usia_u0_sclk@4a0,1 {
+ compatible = "renesas,emev2-smu-gclk";
+ reg = <0x4a0 1>;
+ clocks = <&usia_u0_sclkdiv>;
+ #clock-cells = <0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
deleted file mode 100644
index aed713cf0831..000000000000
--- a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-* Renesas R9A06G032 SYSCTRL
-
-Required Properties:
-
- - compatible: Must be:
- - "renesas,r9a06g032-sysctrl"
- - reg: Base address and length of the SYSCTRL IO block.
- - #clock-cells: Must be 1
- - clocks: References to the parent clocks:
- - external 40mhz crystal.
- - external (optional) 32.768khz
- - external (optional) jtag input
- - external (optional) RGMII_REFCLK
- - clock-names: Must be:
- clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
- - #power-domain-cells: Must be 0
-
-Examples
---------
-
- - SYSCTRL node:
-
- sysctrl: system-controller@4000c000 {
- compatible = "renesas,r9a06g032-sysctrl";
- reg = <0x4000c000 0x1000>;
- #clock-cells = <1>;
-
- clocks = <&ext_mclk>, <&ext_rtc_clk>,
- <&ext_jtag_clk>, <&ext_rgmii_ref>;
- clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
- #power-domain-cells = <0>;
- };
-
- - Other nodes can use the clocks provided by SYSCTRL as in:
-
- #include <dt-bindings/clock/r9a06g032-sysctrl.h>
- uart0: serial@40060000 {
- compatible = "snps,dw-apb-uart";
- reg = <0x40060000 0x400>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- reg-shift = <2>;
- reg-io-width = <4>;
- clocks = <&sysctrl R9A06G032_CLK_UART0>, <&sysctrl R9A06G032_HCLK_UART0>;
- clock-names = "baudclk", "apb_pclk";
- power-domains = <&sysctrl>;
- };
diff --git a/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml
new file mode 100644
index 000000000000..25dbb0fac065
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r9a06g032-sysctrl.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/renesas,r9a06g032-sysctrl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas RZ/N1D (R9A06G032) System Controller
+
+maintainers:
+ - Gareth Williams <gareth.williams.jx@renesas.com>
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+
+properties:
+ compatible:
+ const: renesas,r9a06g032-sysctrl
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ items:
+ - description: External 40 MHz crystal
+ - description: Optional external 32.768 kHz crystal
+ - description: Optional external JTAG input
+ - description: Optional external RGMII_REFCLK
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: mclk
+ - const: rtc
+ - const: jtag
+ - const: rgmii_ref_ext
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ sysctrl: system-controller@4000c000 {
+ compatible = "renesas,r9a06g032-sysctrl";
+ reg = <0x4000c000 0x1000>;
+ clocks = <&ext_mclk>, <&ext_rtc_clk>, <&ext_jtag_clk>,
+ <&ext_rgmii_ref>;
+ clock-names = "mclk", "rtc", "jtag", "rgmii_ref_ext";
+ #clock-cells = <1>;
+ #power-domain-cells = <0>;
+ };
diff --git a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
index 4069e09cb62d..47e1ab08c95d 100644
--- a/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
+++ b/Documentation/devicetree/bindings/clock/sprd,sc9863a-clk.yaml
@@ -40,7 +40,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 4
items:
- const: ext-26m
- const: ext-32k
diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt b/Documentation/devicetree/bindings/clock/ti,sci-clk.txt
deleted file mode 100644
index 4e59dc6b1778..000000000000
--- a/Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+++ /dev/null
@@ -1,36 +0,0 @@
-Texas Instruments TI-SCI Clocks
-===============================
-
-All clocks on Texas Instruments' SoCs that contain a System Controller,
-are only controlled by this entity. Communication between a host processor
-running an OS and the System Controller happens through a protocol known
-as TI-SCI[1]. This clock implementation plugs into the common clock
-framework and makes use of the TI-SCI protocol on clock API requests.
-
-[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-Required properties:
--------------------
-- compatible: Must be "ti,k2g-sci-clk"
-- #clock-cells: Shall be 2.
- In clock consumers, this cell represents the device ID and clock ID
- exposed by the PM firmware. The list of valid values for the device IDs
- and clocks IDs for 66AK2G SoC are documented at
- http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
-
-Examples:
---------
-
-pmmc: pmmc {
- compatible = "ti,k2g-sci";
-
- k2g_clks: clocks {
- compatible = "ti,k2g-sci-clk";
- #clock-cells = <2>;
- };
-};
-
-uart0: serial@2530c00 {
- compatible = "ns16550a";
- clocks = <&k2g_clks 0x2c 0>;
-};
diff --git a/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
new file mode 100644
index 000000000000..0e370289a053
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/ti,sci-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI clock controller node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This clock controller node uses the TI SCI protocol to perform various clock
+ management of various hardware modules (devices) present on the SoC. This
+ node must be a child node of the associated TI-SCI system controller node.
+
+properties:
+ $nodename:
+ pattern: "^clock-controller$"
+
+ compatible:
+ const: ti,k2g-sci-clk
+
+ "#clock-cells":
+ const: 2
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell should contain the clock ID.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+additionalProperties: false
+
+examples:
+ - |
+ k3_clks: clock-controller {
+ compatible = "ti,k2g-sci-clk";
+ #clock-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
index 6ab07eba7778..00648f9d9278 100644
--- a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
+++ b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml
@@ -30,7 +30,6 @@ properties:
- description: Module clock
- description: MBus clock
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -38,7 +37,6 @@ properties:
- const: mod
- const: ram
minItems: 2
- maxItems: 3
resets:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml b/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml
new file mode 100644
index 000000000000..9c97874a6dbd
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/arm,cryptocell.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/arm,cryptocell.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm TrustZone CryptoCell cryptographic engine
+
+maintainers:
+ - Gilad Ben-Yossef <gilad@benyossef.com>
+
+properties:
+ compatible:
+ enum:
+ - arm,cryptocell-713-ree
+ - arm,cryptocell-703-ree
+ - arm,cryptocell-712-ree
+ - arm,cryptocell-710-ree
+ - arm,cryptocell-630p-ree
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ arm_cc712: crypto@80000000 {
+ compatible = "arm,cryptocell-712-ree";
+ reg = <0x80000000 0x10000>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ };
diff --git a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt b/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt
deleted file mode 100644
index 6130e6eb4af8..000000000000
--- a/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Arm TrustZone CryptoCell cryptographic engine
-
-Required properties:
-- compatible: Should be one of -
- "arm,cryptocell-713-ree"
- "arm,cryptocell-703-ree"
- "arm,cryptocell-712-ree"
- "arm,cryptocell-710-ree"
- "arm,cryptocell-630p-ree"
-- reg: Base physical address of the engine and length of memory mapped region.
-- interrupts: Interrupt number for the device.
-
-Optional properties:
-- clocks: Reference to the crypto engine clock.
-- dma-coherent: Present if dma operations are coherent.
-
-Examples:
-
- arm_cc712: crypto@80000000 {
- compatible = "arm,cryptocell-712-ree";
- interrupt-parent = <&intc>;
- interrupts = < 0 30 4 >;
- reg = < 0x80000000 0x10000 >;
-
- };
diff --git a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml
index a30bf38a4a49..99be01539fcd 100644
--- a/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml
+++ b/Documentation/devicetree/bindings/crypto/fsl-dcp.yaml
@@ -27,7 +27,6 @@ properties:
- description: MXS DCP DCP interrupt
- description: MXS DCP secure interrupt
minItems: 2
- maxItems: 3
clocks:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml
index 12a7df0e38b2..3d8ea3c2d8dd 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-backend.yaml
@@ -26,14 +26,12 @@ properties:
reg:
minItems: 1
- maxItems: 2
items:
- description: Display Backend registers
- description: SAT registers
reg-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
@@ -43,7 +41,6 @@ properties:
clocks:
minItems: 3
- maxItems: 4
items:
- description: The backend interface clock
- description: The backend module clock
@@ -52,7 +49,6 @@ properties:
clock-names:
minItems: 3
- maxItems: 4
items:
- const: ahb
- const: mod
@@ -61,14 +57,12 @@ properties:
resets:
minItems: 1
- maxItems: 2
items:
- description: The Backend reset line
- description: The SAT reset line
reset-names:
minItems: 1
- maxItems: 2
items:
- const: be
- const: sat
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
index a738d7c12a97..bf0bdf54e5f9 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun6i-a31-mipi-dsi.yaml
@@ -24,7 +24,6 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
index 907fb47cc84a..5d42d36608d9 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml
@@ -46,7 +46,6 @@ properties:
clocks:
minItems: 3
- maxItems: 6
items:
- description: Bus Clock
- description: Register Clock
@@ -57,7 +56,6 @@ properties:
clock-names:
minItems: 3
- maxItems: 6
items:
- const: iahb
- const: isfr
@@ -68,14 +66,12 @@ properties:
resets:
minItems: 1
- maxItems: 2
items:
- description: HDMI Controller Reset
- description: HDCP Reset
reset-names:
minItems: 1
- maxItems: 2
items:
- const: ctrl
- const: hdcp
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
index 501cec16168c..a97366aaf924 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-hdmi-phy.yaml
@@ -27,7 +27,6 @@ properties:
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
@@ -36,7 +35,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 4
items:
- const: bus
- const: mod
diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
index ec21e8bf2767..61ef7b337218 100644
--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
+++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-r40-tcon-top.yaml
@@ -48,7 +48,6 @@ properties:
clocks:
minItems: 2
- maxItems: 6
items:
- description: The TCON TOP interface clock
- description: The TCON TOP TV0 clock
@@ -59,7 +58,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 6
items:
- const: bus
- const: tcon-tv0
diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
deleted file mode 100644
index 659523f538bf..000000000000
--- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
+++ /dev/null
@@ -1,143 +0,0 @@
-Analog Devices ADV7511(W)/13/33/35 HDMI Encoders
-------------------------------------------------
-
-The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video
-transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space
-conversion, S/PDIF, CEC and HDCP. ADV7533/5 supports the DSI interface for input
-pixels, while the others support RGB interface.
-
-Required properties:
-
-- compatible: Should be one of:
- "adi,adv7511"
- "adi,adv7511w"
- "adi,adv7513"
- "adi,adv7533"
- "adi,adv7535"
-
-- reg: I2C slave addresses
- The ADV7511 internal registers are split into four pages exposed through
- different I2C addresses, creating four register maps. Each map has it own
- I2C address and acts as a standard slave device on the I2C bus. The main
- address is mandatory, others are optional and revert to defaults if not
- specified.
-
-
-The ADV7511 supports a large number of input data formats that differ by their
-color depth, color format, clock mode, bit justification and random
-arrangement of components on the data bus. The combination of the following
-properties describe the input and map directly to the video input tables of the
-ADV7511 datasheet that document all the supported combinations.
-
-- adi,input-depth: Number of bits per color component at the input (8, 10 or
- 12).
-- adi,input-colorspace: The input color space, one of "rgb", "yuv422" or
- "yuv444".
-- adi,input-clock: The input clock type, one of "1x" (one clock cycle per
- pixel), "2x" (two clock cycles per pixel), "ddr" (one clock cycle per pixel,
- data driven on both edges).
-
-The following input format properties are required except in "rgb 1x" and
-"yuv444 1x" modes, in which case they must not be specified.
-
-- adi,input-style: The input components arrangement variant (1, 2 or 3), as
- listed in the input format tables in the datasheet.
-- adi,input-justification: The input bit justification ("left", "evenly",
- "right").
-
-- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
-- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
-- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
-- dvdd-3v-supply: A 3.3V supply that powers up the pin called DVDD_3V
- on the chip.
-- bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is
- needed only for ADV7511.
-
-The following properties are required for ADV7533 and ADV7535:
-
-- adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should
- be one of 1, 2, 3 or 4.
-- a2vdd-supply: 1.8V supply that powers up the A2VDD pin on the chip.
-- v3p3-supply: A 3.3V supply that powers up the V3P3 pin on the chip.
-- v1p2-supply: A supply that powers up the V1P2 pin on the chip. It can be
- either 1.2V or 1.8V for ADV7533 but only 1.8V for ADV7535.
-
-Optional properties:
-
-- interrupts: Specifier for the ADV7511 interrupt
-- pd-gpios: Specifier for the GPIO connected to the power down signal
-
-- adi,clock-delay: Video data clock delay relative to the pixel clock, in ps
- (-1200 ps .. 1600 ps). Defaults to no delay.
-- adi,embedded-sync: The input uses synchronization signals embedded in the
- data stream (similar to BT.656). Defaults to separate H/V synchronization
- signals.
-- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the
- internal timing generator. The chip will rely on the sync signals in the
- DSI data lanes, rather than generate its own timings for HDMI output.
-- clocks: from common clock binding: reference to the CEC clock.
-- clock-names: from common clock binding: must be "cec".
-- reg-names : Names of maps with programmable addresses.
- It can contain any map needing a non-default address.
- Possible maps names are : "main", "edid", "cec", "packet"
-
-Required nodes:
-
-The ADV7511 has two video ports. Their connections are modelled using the OF
-graph bindings specified in Documentation/devicetree/bindings/graph.txt.
-
-- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533/5, the
- remote endpoint phandle should be a reference to a valid mipi_dsi_host device
- node.
-- Video port 1 for the HDMI output
-- Audio port 2 for the HDMI audio input
-
-
-Example
--------
-
- adv7511w: hdmi@39 {
- compatible = "adi,adv7511w";
- /*
- * The EDID page will be accessible on address 0x66 on the I2C
- * bus. All other maps continue to use their default addresses.
- */
- reg = <0x39>, <0x66>;
- reg-names = "main", "edid";
- interrupt-parent = <&gpio3>;
- interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
- clocks = <&cec_clock>;
- clock-names = "cec";
-
- adi,input-depth = <8>;
- adi,input-colorspace = "rgb";
- adi,input-clock = "1x";
- adi,input-style = <1>;
- adi,input-justification = "evenly";
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- adv7511w_in: endpoint {
- remote-endpoint = <&dpi_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- adv7511_out: endpoint {
- remote-endpoint = <&hdmi_connector_in>;
- };
- };
-
- port@2 {
- reg = <2>;
- codec_endpoint: endpoint {
- remote-endpoint = <&i2s0_cpu_endpoint>;
- };
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
new file mode 100644
index 000000000000..d3dd7a79b909
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.yaml
@@ -0,0 +1,240 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/adi,adv7511.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADV7511/11W/13 HDMI Encoders
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ The ADV7511, ADV7511W and ADV7513 are HDMI audio and video
+ transmitters compatible with HDMI 1.4 and DVI 1.0. They support color
+ space conversion, S/PDIF, CEC and HDCP. The transmitter input is
+ parallel RGB or YUV data.
+
+properties:
+ compatible:
+ enum:
+ - adi,adv7511
+ - adi,adv7511w
+ - adi,adv7513
+
+ reg:
+ description: |
+ I2C slave addresses.
+
+ The ADV7511/11W/13 internal registers are split into four pages
+ exposed through different I2C addresses, creating four register
+ maps. Each map has it own I2C address and acts as a standard slave
+ device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ description:
+ Names of maps with programmable addresses. It can contain any map
+ needing a non-default address.
+ minItems: 1
+ items:
+ - const: main
+ - const: edid
+ - const: cec
+ - const: packet
+
+ clocks:
+ description: Reference to the CEC clock.
+ maxItems: 1
+
+ clock-names:
+ const: cec
+
+ interrupts:
+ maxItems: 1
+
+ pd-gpios:
+ description: GPIO connected to the power down signal.
+ maxItems: 1
+
+ avdd-supply:
+ description: A 1.8V supply that powers up the AVDD pin.
+
+ dvdd-supply:
+ description: A 1.8V supply that powers up the DVDD pin.
+
+ pvdd-supply:
+ description: A 1.8V supply that powers up the PVDD pin.
+
+ dvdd-3v-supply:
+ description: A 3.3V supply that powers up the DVDD_3V pin.
+
+ bgvdd-supply:
+ description: A 1.8V supply that powers up the BGVDD pin.
+
+ adi,input-depth:
+ description: Number of bits per color component at the input.
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 8, 10, 12 ]
+
+ adi,input-colorspace:
+ description: Input color space.
+ enum: [ rgb, yuv422, yuv444 ]
+
+ adi,input-clock:
+ description: |
+ Input clock type.
+ "1x": one clock cycle per pixel
+ "2x": two clock cycles per pixel
+ "dd": one clock cycle per pixel, data driven on both edges
+ enum: [ 1x, 2x, dd ]
+
+ adi,clock-delay:
+ description:
+ Video data clock delay relative to the pixel clock, in ps
+ (-1200ps .. 1600 ps).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ adi,embedded-sync:
+ description:
+ If defined, the input uses synchronization signals embedded in the
+ data stream (similar to BT.656).
+ type: boolean
+
+ adi,input-style:
+ description:
+ Input components arrangement variant as listed in the input
+ format tables in the datasheet.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3 ]
+
+ adi,input-justification:
+ description: Input bit justification.
+ enum: [ left, evenly, right ]
+
+ ports:
+ description:
+ The ADV7511(W)/13 has two video ports and one audio port. This node
+ models their connections as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ type: object
+ properties:
+ port@0:
+ description: Video port for the RGB or YUV input.
+ type: object
+
+ port@1:
+ description: Video port for the HDMI output.
+ type: object
+
+ port@2:
+ description: Audio port for the HDMI output.
+ type: object
+
+# adi,input-colorspace and adi,input-clock are required except in
+# "rgb 1x" and "yuv444 1x" modes, in which case they must not be
+# specified.
+if:
+ not:
+ properties:
+ adi,input-colorspace:
+ contains:
+ enum: [ rgb, yuv444 ]
+ adi,input-clock:
+ contains:
+ const: 1x
+
+then:
+ required:
+ - adi,input-style
+ - adi,input-justification
+
+else:
+ properties:
+ adi,input-style: false
+ adi,input-justification: false
+
+
+required:
+ - compatible
+ - reg
+ - ports
+ - adi,input-depth
+ - adi,input-colorspace
+ - adi,input-clock
+ - avdd-supply
+ - dvdd-supply
+ - pvdd-supply
+ - dvdd-3v-supply
+ - bgvdd-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe6500000>;
+
+ adv7511w: hdmi@39 {
+ compatible = "adi,adv7511w";
+ /*
+ * The EDID page will be accessible on address 0x66 on the I2C
+ * bus. All other maps continue to use their default addresses.
+ */
+ reg = <0x39>, <0x66>;
+ reg-names = "main", "edid";
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+ avdd-supply = <&v1v8>;
+ dvdd-supply = <&v1v8>;
+ pvdd-supply = <&v1v8>;
+ dvdd-3v-supply = <&v3v3>;
+ bgvdd-supply = <&v1v8>;
+
+ adi,input-depth = <8>;
+ adi,input-colorspace = "yuv422";
+ adi,input-clock = "1x";
+
+ adi,input-style = <3>;
+ adi,input-justification = "right";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7511w_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7511_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml
new file mode 100644
index 000000000000..f36209137c8a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7533.yaml
@@ -0,0 +1,184 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/adi,adv7533.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices ADV7533/35 HDMI Encoders
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ The ADV7533 and ADV7535 are HDMI audio and video transmitters
+ compatible with HDMI 1.4 and DVI 1.0. They support color space
+ conversion, S/PDIF, CEC and HDCP. The transmitter input is MIPI DSI.
+
+properties:
+ compatible:
+ enum:
+ - adi,adv7533
+ - adi,adv7535
+
+ reg:
+ description: |
+ I2C slave addresses.
+
+ The ADV7533/35 internal registers are split into four pages
+ exposed through different I2C addresses, creating four register
+ maps. Each map has it own I2C address and acts as a standard slave
+ device on the I2C bus. The main address is mandatory, others are
+ optional and revert to defaults if not specified.
+ minItems: 1
+ maxItems: 4
+
+ reg-names:
+ description:
+ Names of maps with programmable addresses. It can contain any map
+ needing a non-default address.
+ minItems: 1
+ items:
+ - const: main
+ - const: edid
+ - const: cec
+ - const: packet
+
+ clocks:
+ description: Reference to the CEC clock.
+ maxItems: 1
+
+ clock-names:
+ const: cec
+
+ interrupts:
+ maxItems: 1
+
+ pd-gpios:
+ description: GPIO connected to the power down signal.
+ maxItems: 1
+
+ avdd-supply:
+ description: A 1.8V supply that powers up the AVDD pin.
+
+ dvdd-supply:
+ description: A 1.8V supply that powers up the DVDD pin.
+
+ pvdd-supply:
+ description: A 1.8V supply that powers up the PVDD pin.
+
+ a2vdd-supply:
+ description: A 1.8V supply that powers up the A2VDD pin.
+
+ v3p3-supply:
+ description: A 3.3V supply that powers up the V3P3 pin.
+
+ v1p2-supply:
+ description:
+ A supply that powers up the V1P2 pin. It can be either 1.2V
+ or 1.8V for ADV7533 but only 1.8V for ADV7535.
+
+ adi,disable-timing-generator:
+ description:
+ Disables the internal timing generator. The chip will rely on the
+ sync signals in the DSI data lanes, rather than generating its own
+ timings for HDMI output.
+ type: boolean
+
+ adi,dsi-lanes:
+ description: Number of DSI data lanes connected to the DSI host.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 3, 4 ]
+
+ ports:
+ description:
+ The ADV7533/35 has two video ports and one audio port. This node
+ models their connections as documented in
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+ Documentation/devicetree/bindings/graph.txt
+ type: object
+ properties:
+ port@0:
+ description:
+ Video port for the DSI input. The remote endpoint phandle
+ should be a reference to a valid mipi_dsi_host_device.
+ type: object
+
+ port@1:
+ description: Video port for the HDMI output.
+ type: object
+
+ port@2:
+ description: Audio port for the HDMI output.
+ type: object
+
+required:
+ - compatible
+ - reg
+ - ports
+ - adi,dsi-lanes
+ - avdd-supply
+ - dvdd-supply
+ - pvdd-supply
+ - a2vdd-supply
+ - v3p3-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c@e6500000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <0 0xe6500000>;
+
+ adv7533: hdmi@39 {
+ compatible = "adi,adv7533";
+ /*
+ * The EDID page will be accessible on address 0x66 on the I2C
+ * bus. All other maps continue to use their default addresses.
+ */
+ reg = <0x39>, <0x66>;
+ reg-names = "main", "edid";
+ interrupt-parent = <&gpio3>;
+ interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
+ clocks = <&cec_clock>;
+ clock-names = "cec";
+ adi,dsi-lanes = <4>;
+ avdd-supply = <&v1v8>;
+ dvdd-supply = <&v1v8>;
+ pvdd-supply = <&v1v8>;
+ a2vdd-supply = <&v1v8>;
+ v3p3-supply = <&v3v3>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ adv7533_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ adv7533_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ codec_endpoint: endpoint {
+ remote-endpoint = <&i2s0_cpu_endpoint>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
index 2333fdbe9296..b2e8bc6da9d0 100644
--- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml
@@ -18,7 +18,6 @@ properties:
reg:
minItems: 1
- maxItems: 3
items:
- description:
Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
@@ -31,7 +30,6 @@ properties:
reg-names:
minItems: 1
- maxItems: 3
items:
- const: mhdptx
- const: j721e-intg
diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
index 735d0233a7d6..674891ee2f8e 100644
--- a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912b.yaml
@@ -29,7 +29,8 @@ properties:
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description:
Primary MIPI port for MIPI input
diff --git a/Documentation/devicetree/bindings/display/panel/lvds.yaml b/Documentation/devicetree/bindings/display/panel/lvds.yaml
index 31164608ba1d..49460c9dceea 100644
--- a/Documentation/devicetree/bindings/display/panel/lvds.yaml
+++ b/Documentation/devicetree/bindings/display/panel/lvds.yaml
@@ -51,37 +51,37 @@ properties:
- "jeida-18" - 18-bit data mapping compatible with the [JEIDA], [LDI] and
[VESA] specifications. Data are transferred as follows on 3 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
- "jeida-24" - 24-bit data mapping compatible with the [DSIM] and [LDI]
specifications. Data are transferred as follows on 4 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
- DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
- DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G2__><__R7__><__R6__><__R5__><__R4__><__R3__><__R2__><
+ DATA1 ><__B3__><__B2__><__G7__><__G6__><__G5__><__G4__><__G3__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B7__><__B6__><__B5__><__B4__><
+ DATA3 ><_CTL3_><__B1__><__B0__><__G1__><__G0__><__R1__><__R0__><
- "vesa-24" - 24-bit data mapping compatible with the [VESA] specification.
Data are transferred as follows on 4 LVDS lanes.
- Slot 0 1 2 3 4 5 6
- ________________ _________________
- Clock \_______________________/
- ______ ______ ______ ______ ______ ______ ______
- DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
- DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
- DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
- DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
+ Slot 0 1 2 3 4 5 6
+ ________________ _________________
+ Clock \_______________________/
+ ______ ______ ______ ______ ______ ______ ______
+ DATA0 ><__G0__><__R5__><__R4__><__R3__><__R2__><__R1__><__R0__><
+ DATA1 ><__B1__><__B0__><__G5__><__G4__><__G3__><__G2__><__G1__><
+ DATA2 ><_CTL2_><_CTL1_><_CTL0_><__B5__><__B4__><__B3__><__B2__><
+ DATA3 ><_CTL3_><__B7__><__B6__><__G7__><__G6__><__R7__><__R6__><
Control signals are mapped as follows.
diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
index 121596f106da..5f4345d43020 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
@@ -55,7 +55,7 @@ properties:
maxItems: 1
ports:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/properties/ports
description: |
The connections to the DU output video ports are modeled using the OF
graph bindings specified in Documentation/devicetree/bindings/graph.txt.
diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 75cd9c686e98..da3b889ad8fc 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -29,7 +29,6 @@ properties:
clocks:
minItems: 2
- maxItems: 5
items:
- {}
- {}
@@ -41,7 +40,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 5
items:
- {}
- {}
diff --git a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
index 679daed4124e..ed310bbe3afe 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
+++ b/Documentation/devicetree/bindings/display/st,stm32-dsi.yaml
@@ -29,7 +29,6 @@ properties:
- description: DSI bus clock
- description: Pixel clock
minItems: 2
- maxItems: 3
clock-names:
items:
@@ -37,7 +36,6 @@ properties:
- const: ref
- const: px_clk
minItems: 2
- maxItems: 3
resets:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
index d54f9ca207af..4ae3d75492d3 100644
--- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml
@@ -22,7 +22,6 @@ properties:
- description: events interrupt line.
- description: errors interrupt line.
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
index 403d57977ee7..d88bd93f4b80 100644
--- a/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
+++ b/Documentation/devicetree/bindings/display/xlnx/xlnx,zynqmp-dpsub.yaml
@@ -65,7 +65,6 @@ properties:
The APB clock and at least one video clock are mandatory, the audio clock
is optional.
minItems: 2
- maxItems: 4
items:
- description: dp_apb_clk is the APB clock
- description: dp_aud_clk is the Audio clock
@@ -78,13 +77,11 @@ properties:
clock-names:
oneOf:
- minItems: 2
- maxItems: 3
items:
- const: dp_apb_clk
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- enum: [ dp_vtc_pixel_clk_in, dp_live_video_in_clk ]
- minItems: 3
- maxItems: 4
items:
- const: dp_apb_clk
- const: dp_aud_clk
@@ -116,7 +113,6 @@ properties:
maxItems: 2
phy-names:
minItems: 1
- maxItems: 2
items:
- const: dp-phy0
- const: dp-phy1
diff --git a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
index 7f2a54bc732d..d8142cbd13d3 100644
--- a/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
+++ b/Documentation/devicetree/bindings/dma/renesas,rcar-dmac.yaml
@@ -52,7 +52,6 @@ properties:
interrupt-names:
minItems: 9
- maxItems: 17
items:
- const: error
- pattern: "^ch([0-9]|1[0-5])$"
diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt
index 29fcd37082e8..f719e1612b0a 100644
--- a/Documentation/devicetree/bindings/dma/ti-edma.txt
+++ b/Documentation/devicetree/bindings/dma/ti-edma.txt
@@ -33,7 +33,7 @@ The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
-------------------
@@ -70,7 +70,7 @@ The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
-------------------
diff --git a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml
index 57e5270a0741..4cfc3a187004 100644
--- a/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml
+++ b/Documentation/devicetree/bindings/edac/amazon,al-mc-edac.yaml
@@ -30,14 +30,12 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: uncorrectable error interrupt
- description: correctable error interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: ue
- const: ce
diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml
index 021d8ae42da3..914a423ec449 100644
--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
+++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
@@ -32,7 +32,6 @@ properties:
oneOf:
- allOf:
- minItems: 1
- maxItems: 2
items:
- pattern: "^(atmel|catalyst|microchip|nxp|ramtron|renesas|rohm|st),(24(c|cs|lc|mac)[0-9]+|spd)$"
- pattern: "^atmel,(24(c|cs|mac)[0-9]+|spd)$"
diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml
index a97f39109f8d..ff6ec65145cf 100644
--- a/Documentation/devicetree/bindings/example-schema.yaml
+++ b/Documentation/devicetree/bindings/example-schema.yaml
@@ -91,7 +91,6 @@ properties:
interrupts:
# Either 1 or 2 interrupts can be present
minItems: 1
- maxItems: 2
items:
- description: tx or combined interrupt
- description: rx interrupt
@@ -105,7 +104,6 @@ properties:
interrupt-names:
# minItems must be specified here because the default would be 2
minItems: 1
- maxItems: 2
items:
- const: tx irq
- const: rx irq
diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
new file mode 100644
index 000000000000..cebf6ffe70d5
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml
@@ -0,0 +1,341 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2021 ARM Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,scmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Control and Management Interface (SCMI) Message Protocol bindings
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |
+ The SCMI is intended to allow agents such as OSPM to manage various functions
+ that are provided by the hardware platform it is running on, including power
+ and performance functions.
+
+ This binding is intended to define the interface the firmware implementing
+ the SCMI as described in ARM document number ARM DEN 0056 ("ARM System Control
+ and Management Interface Platform Design Document")[0] provide for OSPM in
+ the device tree.
+
+ [0] https://developer.arm.com/documentation/den0056/latest
+
+properties:
+ $nodename:
+ const: scmi
+
+ compatible:
+ oneOf:
+ - description: SCMI compliant firmware with mailbox transport
+ items:
+ - const: arm,scmi
+ - description: SCMI compliant firmware with ARM SMC/HVC transport
+ items:
+ - const: arm,scmi-smc
+
+ interrupts:
+ description:
+ The interrupt that indicates message completion by the platform
+ rather than by the return of the smc call. This should not be used
+ except when the platform requires such behavior.
+ maxItems: 1
+
+ interrupt-names:
+ const: a2p
+
+ mbox-names:
+ description:
+ Specifies the mailboxes used to communicate with SCMI compliant
+ firmware.
+ items:
+ - const: tx
+ - const: rx
+
+ mboxes:
+ description:
+ List of phandle and mailbox channel specifiers. It should contain
+ exactly one or two mailboxes, one for transmitting messages("tx")
+ and another optional for receiving the notifications("rx") if supported.
+ minItems: 1
+ maxItems: 2
+
+ shmem:
+ description:
+ List of phandle pointing to the shared memory(SHM) area, for each
+ transport channel specified.
+ minItems: 1
+ maxItems: 2
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ arm,smc-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ SMC id required when using smc or hvc transports
+
+ protocol@11:
+ type: object
+ properties:
+ reg:
+ const: 0x11
+
+ '#power-domain-cells':
+ const: 1
+
+ required:
+ - '#power-domain-cells'
+
+ protocol@13:
+ type: object
+ properties:
+ reg:
+ const: 0x13
+
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ protocol@14:
+ type: object
+ properties:
+ reg:
+ const: 0x14
+
+ '#clock-cells':
+ const: 1
+
+ required:
+ - '#clock-cells'
+
+ protocol@15:
+ type: object
+ properties:
+ reg:
+ const: 0x15
+
+ '#thermal-sensor-cells':
+ const: 1
+
+ required:
+ - '#thermal-sensor-cells'
+
+ protocol@16:
+ type: object
+ properties:
+ reg:
+ const: 0x16
+
+ '#reset-cells':
+ const: 1
+
+ required:
+ - '#reset-cells'
+
+ protocol@17:
+ type: object
+ properties:
+ reg:
+ const: 0x17
+
+ regulators:
+ type: object
+ description:
+ The list of all regulators provided by this SCMI controller.
+
+ patternProperties:
+ '^regulators@[0-9a-f]+$':
+ type: object
+ $ref: "../regulator/regulator.yaml#"
+
+ properties:
+ reg:
+ maxItems: 1
+ description: Identifier for the voltage regulator.
+
+ required:
+ - reg
+
+additionalProperties: false
+
+patternProperties:
+ '^protocol@[0-9a-f]+$':
+ type: object
+ description:
+ Each sub-node represents a protocol supported. If the platform
+ supports a dedicated communication channel for a particular protocol,
+ then the corresponding transport properties must be present.
+
+ properties:
+ reg:
+ maxItems: 1
+
+ mbox-names:
+ items:
+ - const: tx
+ - const: rx
+
+ mboxes:
+ minItems: 1
+ maxItems: 2
+
+ shmem:
+ minItems: 1
+ maxItems: 2
+
+ required:
+ - reg
+
+required:
+ - compatible
+ - shmem
+
+if:
+ properties:
+ compatible:
+ contains:
+ const: arm,scmi
+then:
+ properties:
+ interrupts: false
+ interrupt-names: false
+
+ required:
+ - mboxes
+
+else:
+ if:
+ properties:
+ compatible:
+ contains:
+ const: arm,scmi-smc
+ then:
+ required:
+ - arm,smc-id
+
+examples:
+ - |
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mhuB 0 0>,
+ <&mhuB 0 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>,
+ <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+
+ mboxes = <&mhuB 1 0>,
+ <&mhuB 1 1>;
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_hpri0>,
+ <&cpu_scp_hpri1>;
+ };
+
+ scmi_clk: protocol@14 {
+ reg = <0x14>;
+ #clock-cells = <1>;
+ };
+
+ scmi_sensors: protocol@15 {
+ reg = <0x15>;
+ #thermal-sensor-cells = <1>;
+ };
+
+ scmi_reset: protocol@16 {
+ reg = <0x16>;
+ #reset-cells = <1>;
+ };
+
+ scmi_voltage: protocol@17 {
+ reg = <0x17>;
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ regulator_devX: regulator@0 {
+ reg = <0x0>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ regulator_devY: regulator@9 {
+ reg = <0x9>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <4200000>;
+ };
+ };
+ };
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri0: scp-sram-section@0 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x0 0x80>;
+ };
+
+ cpu_scp_lpri1: scp-sram-section@80 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x80 0x80>;
+ };
+
+ cpu_scp_hpri0: scp-sram-section@100 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x100 0x80>;
+ };
+
+ cpu_scp_hpri2: scp-sram-section@180 {
+ compatible = "arm,scmi-shmem";
+ reg = <0x180 0x80>;
+ };
+ };
+ };
+
+ - |
+ firmware {
+ scmi {
+ compatible = "arm,scmi-smc";
+ shmem = <&cpu_scp_lpri0 &cpu_scp_lpri1>;
+ arm,smc-id = <0xc3000001>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd1: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/firmware/arm,scpi.yaml b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml
new file mode 100644
index 000000000000..d7113b06454b
--- /dev/null
+++ b/Documentation/devicetree/bindings/firmware/arm,scpi.yaml
@@ -0,0 +1,247 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2021 ARM Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/firmware/arm,scpi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: System Control and Power Interface (SCPI) Message Protocol bindings
+
+maintainers:
+ - Sudeep Holla <sudeep.holla@arm.com>
+
+description: |
+ Firmware implementing the SCPI described in ARM document number ARM DUI
+ 0922B ("ARM Compute Subsystem SCP: Message Interface Protocols")[0] can be
+ used by Linux to initiate various system control and power operations.
+
+ This binding is intended to define the interface the firmware implementing
+ the SCPI provide for OSPM in the device tree.
+
+ [0] http://infocenter.arm.com/help/topic/com.arm.doc.dui0922b/index.html
+
+properties:
+ $nodename:
+ const: scpi
+
+ compatible:
+ description:
+ SCPI compliant firmware complying to SCPI v1.0 and above OR
+ SCPI compliant firmware complying to all unversioned releases
+ prior to SCPI v1.0
+ oneOf:
+ - const: arm,scpi # SCPI v1.0 and above
+ - const: arm,scpi-pre-1.0 # Unversioned SCPI before v1.0
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-scpi
+ - const: arm,scpi-pre-1.0
+
+ mboxes:
+ description:
+ List of phandle and mailbox channel specifiers. All the channels reserved
+ by remote SCP firmware for use by SCPI message protocol should be
+ specified in any order.
+ minItems: 1
+
+ shmem:
+ description:
+ List of phandle pointing to the shared memory(SHM) area between the
+ processors using these mailboxes for IPC, one for each mailbox SHM can
+ be any memory reserved for the purpose of this communication between the
+ processors.
+ minItems: 1
+
+ power-controller:
+ type: object
+ description:
+ This sub-node represents SCPI power domain controller.
+
+ properties:
+ compatible:
+ const: arm,scpi-power-domains
+
+ '#power-domain-cells':
+ const: 1
+
+ num-domains:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Total number of power domains provided by SCPI. This is needed as
+ the SCPI message protocol lacks a mechanism to query this
+ information at runtime.
+
+ required:
+ - compatible
+ - '#power-domain-cells'
+ - num-domains
+
+ additionalProperties: false
+
+ sensors:
+ type: object
+ description: |
+ This sub-node represents SCPI sensors controller.
+
+ properties:
+ compatible:
+ oneOf:
+ - const: arm,scpi-sensors
+ - items:
+ - enum:
+ - amlogic,meson-gxbb-scpi-sensors
+ - const: arm,scpi-sensors
+
+ '#thermal-sensor-cells':
+ const: 1
+
+ required:
+ - compatible
+ - '#thermal-sensor-cells'
+
+ additionalProperties: false
+
+ clocks:
+ type: object
+ description:
+ This is the container node. Each sub-node represents one of the types
+ of clock controller - indexed or full range.
+
+ properties:
+ compatible:
+ const: arm,scpi-clocks
+
+ patternProperties:
+ "^clocks-[0-9a-f]+$":
+ type: object
+ description: |
+ This sub-node represents one of the types of clock controller
+ - indexed or full range.
+
+ "arm,scpi-dvfs-clocks" - all the clocks that are variable and index
+ based. These clocks don't provide an entire range of values between
+ the limits but only discrete points within the range. The firmware
+ provides the mapping for each such operating frequency and the index
+ associated with it. The firmware also manages the voltage scaling
+ appropriately with the clock scaling.
+
+ "arm,scpi-variable-clocks" - all the clocks that are variable and
+ provide full range within the specified range. The firmware provides
+ the range of values within a specified range.
+
+ properties:
+ compatible:
+ oneOf:
+ - const: arm,scpi-dvfs-clocks
+ - const: arm,scpi-variable-clocks
+
+ '#clock-cells':
+ const: 1
+
+ clock-output-names: true
+
+ clock-indices:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ The identifying number for the clocks(i.e.clock_id) in the node.
+ It can be non linear and hence provide the mapping of identifiers
+ into the clock-output-names array.
+
+ required:
+ - compatible
+ - '#clock-cells'
+ - clock-output-names
+ - clock-indices
+
+ additionalProperties: false
+
+ required:
+ - compatible
+
+ additionalProperties: false
+
+additionalProperties: false
+
+required:
+ - compatible
+ - mboxes
+ - shmem
+
+examples:
+ - |
+ firmware {
+ scpi {
+ compatible = "arm,scpi";
+ mboxes = <&mhuA 1>;
+ shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
+
+ scpi_devpd: power-controller {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
+
+ clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: clocks-0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>, <1>, <2>;
+ clock-output-names = "atlclk", "aplclk","gpuclk";
+ };
+
+ scpi_clk: clocks-1 {
+ compatible = "arm,scpi-variable-clocks";
+ #clock-cells = <1>;
+ clock-indices = <3>, <4>;
+ clock-output-names = "pxlclk0", "pxlclk1";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+
+ };
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ sram@50000000 {
+ compatible = "mmio-sram";
+ reg = <0x0 0x50000000 0x0 0x10000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0x50000000 0x10000>;
+
+ cpu_scp_lpri: scp-sram-section@0 {
+ compatible = "arm,scp-shmem";
+ reg = <0x0 0x200>;
+ };
+
+ cpu_scp_hpri: scp-sram-section@200 {
+ compatible = "arm,scp-shmem";
+ reg = <0x200 0x200>;
+ };
+ };
+ };
+
+ - |
+ firmware {
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_sensors1: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
deleted file mode 100644
index 7018aa896835..000000000000
--- a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-Xilinx Zynq FPGA Manager
-
-Required properties:
-- compatible: should contain "xlnx,zynq-devcfg-1.0"
-- reg: base address and size for memory mapped io
-- interrupts: interrupt for the FPGA manager device
-- clocks: phandle for clocks required operation
-- clock-names: name for the clock, should be "ref_clk"
-- syscon: phandle for access to SLCR registers
-
-Example:
- devcfg: devcfg@f8007000 {
- compatible = "xlnx,zynq-devcfg-1.0";
- reg = <0xf8007000 0x100>;
- interrupts = <0 8 4>;
- clocks = <&clkc 12>;
- clock-names = "ref_clk";
- syscon = <&slcr>;
- };
diff --git a/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
new file mode 100644
index 000000000000..29daca4be47f
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xilinx-zynq-fpga-mgr.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xilinx-zynq-fpga-mgr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq FPGA Manager Device Tree Bindings
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+properties:
+ compatible:
+ const: xlnx,zynq-devcfg-1.0
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: ref_clk
+
+ syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to syscon block which provide access to SLCR registers
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - syscon
+
+additionalProperties: false
+
+examples:
+ - |
+ devcfg: devcfg@f8007000 {
+ compatible = "xlnx,zynq-devcfg-1.0";
+ reg = <0xf8007000 0x100>;
+ interrupts = <0 8 4>;
+ clocks = <&clkc 12>;
+ clock-names = "ref_clk";
+ syscon = <&slcr>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
index 696ea46227d1..8ad4fd9aaffd 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-davinci.txt
@@ -32,7 +32,7 @@ Required Properties:
Documentation/devicetree/bindings/clock/keystone-gate.txt
for 66AK2HK/66AK2L/66AK2E SoCs or,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
for 66AK2G SoCs
- clock-names: Name should be "gpio";
diff --git a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
index 9d72264fa90a..e6485f7b046f 100644
--- a/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
+++ b/Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
@@ -34,7 +34,6 @@ properties:
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 2
- maxItems: 4
interrupts:
items:
diff --git a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
index 3ed172629974..93e7244cdc0e 100644
--- a/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
+++ b/Documentation/devicetree/bindings/gpu/vivante,gc.yaml
@@ -36,7 +36,6 @@ properties:
- description: AHB/slave interface clock (only required if GPU can gate
slave interface independently)
minItems: 1
- maxItems: 4
clock-names:
items:
diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
new file mode 100644
index 000000000000..ea643e6c3ef5
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/aspeed,i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED I2C on the AST24XX, AST25XX, and AST26XX SoCs Device Tree Bindings
+
+maintainers:
+ - Rayn Chen <rayn_chen@aspeedtech.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - aspeed,ast2400-i2c-bus
+ - aspeed,ast2500-i2c-bus
+ - aspeed,ast2600-i2c-bus
+
+ reg:
+ minItems: 1
+ items:
+ - description: address offset and range of bus
+ - description: address offset and range of bus buffer
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ root clock of bus, should reference the APB
+ clock in the second cell
+
+ resets:
+ maxItems: 1
+
+ bus-frequency:
+ minimum: 500
+ maximum: 4000000
+ default: 100000
+ description: frequency of the bus clock in Hz defaults to 100 kHz when not
+ specified
+
+ multi-master:
+ type: boolean
+ description:
+ states that there is another master active on this bus
+
+required:
+ - reg
+ - compatible
+ - clocks
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/aspeed-clock.h>
+ i2c0: i2c-bus@40 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #interrupt-cells = <1>;
+ compatible = "aspeed,ast2500-i2c-bus";
+ reg = <0x40 0x40>;
+ clocks = <&syscon ASPEED_CLK_APB>;
+ resets = <&syscon ASPEED_RESET_I2C>;
+ bus-frequency = <100000>;
+ interrupts = <0>;
+ interrupt-parent = <&i2c_ic>;
+ };
diff --git a/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml
index edbca2476128..7070c04469ed 100644
--- a/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/brcm,brcmstb-i2c.yaml
@@ -21,7 +21,6 @@ properties:
reg:
minItems: 1
- maxItems: 2
items:
- description: BSC register range
- description: Auto-I2C register range
diff --git a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt b/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
deleted file mode 100644
index b47f6ccb196a..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-aspeed.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Device tree configuration for the I2C busses on the AST24XX, AST25XX, and AST26XX SoCs.
-
-Required Properties:
-- #address-cells : should be 1
-- #size-cells : should be 0
-- reg : address offset and range of bus
-- compatible : should be "aspeed,ast2400-i2c-bus"
- or "aspeed,ast2500-i2c-bus"
- or "aspeed,ast2600-i2c-bus"
-- clocks : root clock of bus, should reference the APB
- clock in the second cell
-- resets : phandle to reset controller with the reset number in
- the second cell
-- interrupts : interrupt number
-
-Optional Properties:
-- bus-frequency : frequency of the bus clock in Hz defaults to 100 kHz when not
- specified
-- multi-master : states that there is another master active on this bus.
-
-Example:
-
-i2c {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0 0x1e78a000 0x1000>;
-
- i2c_ic: interrupt-controller@0 {
- #interrupt-cells = <1>;
- compatible = "aspeed,ast2400-i2c-ic";
- reg = <0x0 0x40>;
- interrupts = <12>;
- interrupt-controller;
- };
-
- i2c0: i2c-bus@40 {
- #address-cells = <1>;
- #size-cells = <0>;
- #interrupt-cells = <1>;
- reg = <0x40 0x40>;
- compatible = "aspeed,ast2400-i2c-bus";
- clocks = <&syscon ASPEED_CLK_APB>;
- resets = <&syscon ASPEED_RESET_I2C>;
- bus-frequency = <100000>;
- interrupts = <0>;
- interrupt-parent = <&i2c_ic>;
- };
-};
diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
index b745f3706120..6590501c53d4 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt
@@ -8,7 +8,7 @@ Required properties:
- reg : Offset and length of the register set for the device
- clocks: I2C functional clock phandle.
For 66AK2G this property should be set per binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
SoC-specific Required Properties:
@@ -17,7 +17,7 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only:
- power-domains: Should contain a phandle to a PM domain provider node
and an args specifier containing the I2C device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Recommended properties :
- interrupts : standard interrupt property.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt
index 81b5d55086fa..86b2e433a969 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.txt
@@ -27,7 +27,7 @@ Required properties:
- i2c-bus-name: The name of this bus. Also needed as pinctrl-name for the I2C
parents.
-Furthermore, I2C mux properties and child nodes. See i2c-mux.txt in this
+Furthermore, I2C mux properties and child nodes. See i2c-mux.yaml in this
directory.
Example:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
index 21da3ecbb370..e00d2b9e957a 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.txt
@@ -22,8 +22,8 @@ Required properties:
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
- mux-gpios: list of gpios used to control the muxer
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional properties:
- idle-state: value to set the muxer to when idle. When no value is
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt
deleted file mode 100644
index 8b444b94e92f..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.txt
+++ /dev/null
@@ -1,99 +0,0 @@
-General Purpose I2C Bus Mux
-
-This binding describes an I2C bus multiplexer that uses a mux controller
-from the mux subsystem to route the I2C signals.
-
- .-----. .-----.
- | dev | | dev |
- .------------. '-----' '-----'
- | SoC | | |
- | | .--------+--------'
- | .------. | .------+ child bus A, on MUX value set to 0
- | | I2C |-|--| Mux |
- | '------' | '--+---+ child bus B, on MUX value set to 1
- | .------. | | '----------+--------+--------.
- | | MUX- | | | | | |
- | | Ctrl |-|-----+ .-----. .-----. .-----.
- | '------' | | dev | | dev | | dev |
- '------------' '-----' '-----' '-----'
-
-Required properties:
-- compatible: i2c-mux
-- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
- port is connected to.
-- mux-controls: The phandle of the mux controller to use for operating the
- mux.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory. The sub-bus number
- is also the mux-controller state described in ../mux/mux-controller.txt
-
-Optional properties:
-- mux-locked: If present, explicitly allow unrelated I2C transactions on the
- parent I2C adapter at these times:
- + during setup of the multiplexer
- + between setup of the multiplexer and the child bus I2C transaction
- + between the child bus I2C transaction and releasing of the multiplexer
- + during releasing of the multiplexer
- However, I2C transactions to devices behind all I2C multiplexers connected
- to the same parent adapter that this multiplexer is connected to are blocked
- for the full duration of the complete multiplexed I2C transaction (i.e.
- including the times covered by the above list).
- If mux-locked is not present, the multiplexer is assumed to be parent-locked.
- This means that no unrelated I2C transactions are allowed on the parent I2C
- adapter for the complete multiplexed I2C transaction.
- The properties of mux-locked and parent-locked multiplexers are discussed
- in more detail in Documentation/i2c/i2c-topology.rst.
-
-For each i2c child node, an I2C child bus will be created. They will
-be numbered based on their order in the device tree.
-
-Whenever an access is made to a device on a child bus, the value set
-in the relevant node's reg property will be set as the state in the
-mux controller.
-
-Example:
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- mux-locked;
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@1 {
- reg = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- compatible = "solomon,ssd1307fb-i2c";
- reg = <0x3c>;
- pwms = <&pwm 4 3000>;
- reset-gpios = <&gpio2 7 1>;
- reset-active-low;
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml
new file mode 100644
index 000000000000..9b0603a72f40
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpmux.yaml
@@ -0,0 +1,124 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: General Purpose I2C Bus Mux
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ This binding describes an I2C bus multiplexer that uses a mux controller
+ from the mux subsystem to route the I2C signals.
+
+ .-----. .-----.
+ | dev | | dev |
+ .------------. '-----' '-----'
+ | SoC | | |
+ | | .--------+--------'
+ | .------. | .------+ child bus A, on MUX value set to 0
+ | | I2C |-|--| Mux |
+ | '------' | '--+---+ child bus B, on MUX value set to 1
+ | .------. | | '----------+--------+--------.
+ | | MUX- | | | | | |
+ | | Ctrl |-|-----+ .-----. .-----. .-----.
+ | '------' | | dev | | dev | | dev |
+ '------------' '-----' '-----' '-----'
+
+
+
+allOf:
+ - $ref: /schemas/i2c/i2c-mux.yaml#
+
+properties:
+ compatible:
+ const: i2c-mux
+
+ i2c-parent:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the I2C bus that this multiplexer's master-side port is
+ connected to.
+
+ mux-controls:
+ maxItems: 1
+ description:
+ The mux-controller states are the I2C sub-bus numbers.
+
+ mux-locked:
+ type: boolean
+ description: |
+ Explicitly allow unrelated I2C transactions on the parent I2C adapter at
+ these times:
+ - during setup of the multiplexer
+ - between setup of the multiplexer and the child bus I2C transaction
+ - between the child bus I2C transaction and releasing of the multiplexer
+ - during releasing of the multiplexer
+
+ However, I2C transactions to devices behind all I2C multiplexers connected
+ to the same parent adapter that this multiplexer is connected to are blocked
+ for the full duration of the complete multiplexed I2C transaction (i.e.
+ including the times covered by the above list).
+ If mux-locked is not present, the multiplexer is assumed to be parent-locked.
+ This means that no unrelated I2C transactions are allowed on the parent I2C
+ adapter for the complete multiplexed I2C transaction.
+ The properties of mux-locked and parent-locked multiplexers are discussed
+ in more detail in Documentation/i2c/i2c-topology.rst.
+
+required:
+ - compatible
+ - i2c-parent
+ - mux-controls
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ mux-locked;
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt
index 8b1e49cdce3f..29c4550c9782 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-ltc4306.txt
@@ -8,8 +8,8 @@ Required Properties:
The following required properties are defined externally:
- - Standard I2C mux properties. See i2c-mux.txt in this directory.
- - I2C child bus nodes. See i2c-mux.txt in this directory.
+ - Standard I2C mux properties. See i2c-mux.yaml in this directory.
+ - I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional Properties:
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
deleted file mode 100644
index 7abda506b828..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt
+++ /dev/null
@@ -1,74 +0,0 @@
-* NXP PCA954x I2C bus switch
-
-The driver supports NXP PCA954x and PCA984x I2C mux/switch devices.
-
-Required Properties:
-
- - compatible: Must contain one of the following.
- "nxp,pca9540",
- "nxp,pca9542",
- "nxp,pca9543",
- "nxp,pca9544",
- "nxp,pca9545",
- "nxp,pca9546", "nxp,pca9846",
- "nxp,pca9547", "nxp,pca9847",
- "nxp,pca9548", "nxp,pca9848",
- "nxp,pca9849"
-
- - reg: The I2C address of the device.
-
- The following required properties are defined externally:
-
- - Standard I2C mux properties. See i2c-mux.txt in this directory.
- - I2C child bus nodes. See i2c-mux.txt in this directory.
-
-Optional Properties:
-
- - reset-gpios: Reference to the GPIO connected to the reset input.
- - idle-state: if present, overrides i2c-mux-idle-disconnect,
- Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt
- - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all
- children in idle state. This is necessary for example, if there are several
- multiplexers on the bus and the devices behind them use same I2C addresses.
- - interrupts: Interrupt mapping for IRQ.
- - interrupt-controller: Marks the device node as an interrupt controller.
- - #interrupt-cells : Should be two.
- - first cell is the pin number
- - second cell is used to specify flags.
- See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-Example:
-
- i2c-switch@74 {
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x74>;
-
- interrupt-parent = <&ipic>;
- interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
- interrupt-controller;
- #interrupt-cells = <2>;
-
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
-
- eeprom@54 {
- compatible = "atmel,24c08";
- reg = <0x54>;
- };
- };
-
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- rtc@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml
new file mode 100644
index 000000000000..9f1726d0356b
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.yaml
@@ -0,0 +1,110 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux-pca954x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PCA954x I2C bus switch
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description:
+ The binding supports NXP PCA954x and PCA984x I2C mux/switch devices.
+
+allOf:
+ - $ref: /schemas/i2c/i2c-mux.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - nxp,pca9540
+ - nxp,pca9542
+ - nxp,pca9543
+ - nxp,pca9544
+ - nxp,pca9545
+ - nxp,pca9546
+ - nxp,pca9547
+ - nxp,pca9548
+ - nxp,pca9846
+ - nxp,pca9847
+ - nxp,pca9848
+ - nxp,pca9849
+ - items:
+ - const: nxp,pca9646
+ - const: nxp,pca9546
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupt-controller: true
+
+ reset-gpios:
+ maxItems: 1
+
+ i2c-mux-idle-disconnect:
+ type: boolean
+ description: Forces mux to disconnect all children in idle state. This is
+ necessary for example, if there are several multiplexers on the bus and
+ the devices behind them use same I2C addresses.
+
+ idle-state:
+ description: if present, overrides i2c-mux-idle-disconnect
+ $ref: /schemas/mux/mux-controller.yaml#/properties/idle-state
+
+required:
+ - compatible
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@74 {
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+
+ interrupt-parent = <&ipic>;
+ interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ i2c@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ eeprom@54 {
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ };
+
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
index 33119a98e144..997a287ed3f6 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.txt
@@ -28,9 +28,9 @@ Also required are:
* Standard pinctrl properties that specify the pin mux state for each child
bus. See ../pinctrl/pinctrl-bindings.txt.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
For each named state defined in the pinctrl-names property, an I2C child bus
will be created. I2C child bus numbers are assigned based on the index into
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt
index de00d7fc450b..b9d9755e4172 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt
@@ -7,8 +7,8 @@ Required properties:
- compatible: i2c-mux-reg
- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side
port is connected to.
-* Standard I2C mux properties. See i2c-mux.txt in this directory.
-* I2C child bus nodes. See i2c-mux.txt in this directory.
+* Standard I2C mux properties. See i2c-mux.yaml in this directory.
+* I2C child bus nodes. See i2c-mux.yaml in this directory.
Optional properties:
- reg: this pair of <offset size> specifies the register to control the mux.
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.txt b/Documentation/devicetree/bindings/i2c/i2c-mux.txt
deleted file mode 100644
index b38f58a1c878..000000000000
--- a/Documentation/devicetree/bindings/i2c/i2c-mux.txt
+++ /dev/null
@@ -1,73 +0,0 @@
-Common i2c bus multiplexer/switch properties.
-
-An i2c bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner. The nodes for an i2c bus
-multiplexer/switch will have one child node for each child bus.
-
-Optional properties:
-- #address-cells = <1>;
- This property is required if the i2c-mux child node does not exist.
-
-- #size-cells = <0>;
- This property is required if the i2c-mux child node does not exist.
-
-- i2c-mux
- For i2c multiplexers/switches that have child nodes that are a mixture
- of both i2c child busses and other child nodes, the 'i2c-mux' subnode
- can be used for populating the i2c child busses. If an 'i2c-mux'
- subnode is present, only subnodes of this will be considered as i2c
- child busses.
-
-Required properties for the i2c-mux child node:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Required properties for i2c child bus nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-Optional properties for i2c child bus nodes:
-- Other properties specific to the multiplexer/switch hardware.
-- Child nodes conforming to i2c bus binding
-
-
-Example :
-
- /*
- An NXP pca9548 8 channel I2C multiplexer at address 0x70
- with two NXP pca8574 GPIO expanders attached, one each to
- ports 3 and 4.
- */
-
- mux@70 {
- compatible = "nxp,pca9548";
- reg = <0x70>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
-
- gpio1: gpio@38 {
- compatible = "nxp,pca8574";
- reg = <0x38>;
- #gpio-cells = <2>;
- gpio-controller;
- };
- };
- i2c@4 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <4>;
-
- gpio2: gpio@38 {
- compatible = "nxp,pca8574";
- reg = <0x38>;
- #gpio-cells = <2>;
- gpio-controller;
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux.yaml
new file mode 100644
index 000000000000..24cac36037f5
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/i2c-mux.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/i2c-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common i2c bus multiplexer/switch properties.
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ An i2c bus multiplexer/switch will have several child busses that are numbered
+ uniquely in a device dependent manner. The nodes for an i2c bus
+ multiplexer/switch will have one child node for each child bus.
+
+ For i2c multiplexers/switches that have child nodes that are a mixture of both
+ i2c child busses and other child nodes, the 'i2c-mux' subnode can be used for
+ populating the i2c child busses. If an 'i2c-mux' subnode is present, only
+ subnodes of this will be considered as i2c child busses.
+
+properties:
+ $nodename:
+ pattern: '^(i2c-?)?mux'
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^i2c@[0-9a-f]+$':
+ $ref: /schemas/i2c/i2c-controller.yaml
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ description: The mux selector sub-bus number for the child I2C bus.
+ maxItems: 1
+
+additionalProperties: true
+
+examples:
+ - |
+ /*
+ * An NXP pca9548 8 channel I2C multiplexer at address 0x70
+ * with two NXP pca8574 GPIO expanders attached, one each to
+ * ports 3 and 4.
+ */
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c-mux@70 {
+ compatible = "nxp,pca9548";
+ reg = <0x70>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ i2c@4 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+
+ gpio@20 {
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
index eb72dd571def..f771c09aabfc 100644
--- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
+++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml
@@ -43,14 +43,12 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock for the I2C bus
- description: Bus clock (Only for Armada 7K/8K)
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: reg
diff --git a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
index d2b401d062b9..93198d5d43a6 100644
--- a/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
+++ b/Documentation/devicetree/bindings/i2c/mellanox,i2c-mlxbf.yaml
@@ -20,7 +20,6 @@ properties:
reg:
minItems: 3
- maxItems: 4
items:
- description: Smbus block registers
- description: Cause master registers
diff --git a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
index 3be8955587e4..7e8328e9ce13 100644
--- a/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.yaml
@@ -41,7 +41,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 4
items:
- const: clkin
- const: core
diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
index 1e7894e524f9..733351dee252 100644
--- a/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
+++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.yaml
@@ -38,14 +38,12 @@ properties:
dfsdm clock can also feed CLKOUT, when CLKOUT is used.
- description: audio clock can be used as an alternate to feed CLKOUT.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: dfsdm
- const: audio
minItems: 1
- maxItems: 2
"#address-cells":
const: 1
diff --git a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt
deleted file mode 100644
index 89647d714387..000000000000
--- a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-I/O channel multiplexer bindings
-
-If a multiplexer is used to select which hardware signal is fed to
-e.g. an ADC channel, these bindings describe that situation.
-
-Required properties:
-- compatible : "io-channel-mux"
-- io-channels : Channel node of the parent channel that has multiplexed
- input.
-- io-channel-names : Should be "parent".
-- #address-cells = <1>;
-- #size-cells = <0>;
-- mux-controls : Mux controller node to use for operating the mux
-- channels : List of strings, labeling the mux controller states.
-
-For each non-empty string in the channels property, an io-channel will
-be created. The number of this io-channel is the same as the index into
-the list of strings in the channels property, and also matches the mux
-controller state. The mux controller state is described in
-../mux/mux-controller.txt
-
-Example:
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync", "in", "system-regulator";
- };
diff --git a/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml
new file mode 100644
index 000000000000..870b043406d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/multiplexer/io-channel-mux.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: I/O channel multiplexer bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ If a multiplexer is used to select which hardware signal is fed to
+ e.g. an ADC channel, these bindings describe that situation.
+
+ For each non-empty string in the channels property, an io-channel will be
+ created. The number of this io-channel is the same as the index into the list
+ of strings in the channels property, and also matches the mux controller
+ state. The mux controller state is described in
+ Documentation/devicetree/bindings/mux/mux-controller.yaml
+
+properties:
+
+ compatible:
+ const: io-channel-mux
+
+ io-channels:
+ maxItems: 1
+ description: Channel node of the parent channel that has multiplexed input.
+
+ io-channel-names:
+ const: parent
+
+ mux-controls: true
+ mux-control-names: true
+
+ channels:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description:
+ List of strings, labeling the mux controller states.
+
+required:
+ - compatible
+ - io-channels
+ - io-channel-names
+ - mux-controls
+ - channels
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+ channels = "sync", "in", "system-regulator";
+ };
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt
deleted file mode 100644
index dd527216c5fb..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* ARM Vectored Interrupt Controller
-
-One or more Vectored Interrupt Controllers (VIC's) can be connected in an ARM
-system for interrupt routing. For multiple controllers they can either be
-nested or have the outputs wire-OR'd together.
-
-Required properties:
-
-- compatible : should be one of
- "arm,pl190-vic"
- "arm,pl192-vic"
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : The number of cells to define the interrupts. Must be 1 as
- the VIC has no configuration options for interrupt sources. The cell is a u32
- and defines the interrupt number.
-- reg : The register bank for the VIC.
-
-Optional properties:
-
-- interrupts : Interrupt source for parent controllers if the VIC is nested.
-- valid-mask : A one cell big bit mask of valid interrupt sources. Each bit
- represents single interrupt source, starting from source 0 at LSb and ending
- at source 31 at MSb. A bit that is set means that the source is wired and
- clear means otherwise. If unspecified, defaults to all valid.
-- valid-wakeup-mask : A one cell big bit mask of interrupt sources that can be
- configured as wake up source for the system. Order of bits is the same as for
- valid-mask property. A set bit means that this interrupt source can be
- configured as a wake up source for the system. If unspecied, defaults to all
- interrupt sources configurable as wake up sources.
-
-Example:
-
- vic0: interrupt-controller@60000 {
- compatible = "arm,pl192-vic";
- interrupt-controller;
- #interrupt-cells = <1>;
- reg = <0x60000 0x1000>;
-
- valid-mask = <0xffffff7f>;
- valid-wakeup-mask = <0x0000ff7f>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml
new file mode 100644
index 000000000000..0075e72fe8c1
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/arm,vic.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/arm,vic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Vectored Interrupt Controller
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |+
+ One or more Vectored Interrupt Controllers (VIC's) can be connected in an
+ ARM system for interrupt routing. For multiple controllers they can either
+ be nested or have the outputs wire-OR'd together.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - arm,pl190-vic
+ - arm,pl192-vic
+ - arm,versatile-vic
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+ description:
+ The number of cells to define the interrupts. It must be 1 as the
+ VIC has no configuration options for interrupt sources. The single
+ cell defines the interrupt number.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ valid-mask:
+ description:
+ A one cell big bit mask of valid interrupt sources. Each bit
+ represents single interrupt source, starting from source 0 at
+ LSb and ending at source 31 at MSb. A bit that is set means
+ that the source is wired and clear means otherwise. If unspecified,
+ defaults to all valid.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ valid-wakeup-mask:
+ description:
+ A one cell big bit mask of interrupt sources that can be configured
+ as wake up source for the system. Order of bits is the same as for
+ valid-mask property. A set bit means that this interrupt source
+ can be configured as a wake up source for the system. If unspecied,
+ defaults to all interrupt sources configurable as wake up sources.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ // PL192 VIC
+ vic0: interrupt-controller@60000 {
+ compatible = "arm,pl192-vic";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x60000 0x1000>;
+
+ valid-mask = <0xffffff7f>;
+ valid-wakeup-mask = <0x0000ff7f>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
index 3b11a1a15398..bcb5e20fa9ca 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,irqsteer.yaml
@@ -35,7 +35,6 @@ properties:
- description: output interrupt 6
- description: output interrupt 7
minItems: 1
- maxItems: 8
clocks:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
index 067165c4b836..edf26452dc72 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -50,7 +50,6 @@ properties:
- const: int2
- const: int3
minItems: 1
- maxItems: 4
'#interrupt-cells':
const: 2
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
index 9731dd4421a1..051beb45d998 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,pruss-intc.yaml
@@ -134,7 +134,7 @@ examples:
/* AM4376 PRU-ICSS */
#include <dt-bindings/interrupt-controller/arm-gic.h>
pruss@0 {
- compatible = "ti,am4376-pruss";
+ compatible = "ti,am4376-pruss1";
reg = <0x0 0x40000>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 5951c6f98c74..e87bfbcc6913 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -38,7 +38,6 @@ properties:
If provided, then the combined interrupt will be used in preference to
any others.
- minItems: 2
- maxItems: 4
items:
- const: eventq # Event Queue not empty
- const: gerror # Global Error activated
diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
index dda44976acc1..02c69a95c332 100644
--- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -49,7 +49,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
description:
Specifiers for the MMU fault interrupts. Not required for cache IPMMUs.
items:
diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
index d07eb00b97c8..bd49c201477d 100644
--- a/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
+++ b/Documentation/devicetree/bindings/mailbox/arm,mhu.yaml
@@ -101,11 +101,19 @@ examples:
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
+ };
- mhu_client_scb: scb@2e000000 {
- compatible = "fujitsu,mb86s70-scb-1.0";
- reg = <0 0x2e000000 0 0x4000>;
+ firmware {
+ scpi {
+ compatible = "arm,scpi";
mboxes = <&mhuA 1>; /* HP-NonSecure */
+ shmem = <&cpu_scp_hpri>; /* HP-NonSecure */
+
+ scpi_devpd: power-controller {
+ compatible = "arm,scpi-power-domains";
+ num-domains = <2>;
+ #power-domain-cells = <1>;
+ };
};
};
@@ -125,10 +133,36 @@ examples:
clocks = <&clock 0 2 1>;
clock-names = "apb_pclk";
};
+ };
- mhu_client_scpi: scpi@2f000000 {
- compatible = "arm,scpi";
- reg = <0 0x2f000000 0 0x200>;
- mboxes = <&mhuB 1 4>; /* HP-NonSecure, 5th doorbell */
+ firmware {
+ scmi {
+ compatible = "arm,scmi";
+ mboxes = <&mhuB 0 0>, /* LP-NonSecure, 1st doorbell */
+ <&mhuB 0 1>; /* LP-NonSecure, 2nd doorbell */
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_lpri0>,
+ <&cpu_scp_lpri1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ scmi_devpd: protocol@11 {
+ reg = <0x11>;
+ #power-domain-cells = <1>;
+ };
+
+ scmi_dvfs: protocol@13 {
+ reg = <0x13>;
+ #clock-cells = <1>;
+
+ mboxes = <&mhuB 1 2>, /* HP-NonSecure, 3rd doorbell */
+ <&mhuB 1 3>; /* HP-NonSecure, 4th doorbell */
+ mbox-names = "tx", "rx";
+ shmem = <&cpu_scp_hpri0>,
+ <&cpu_scp_hpri1>;
+ };
};
};
+
+...
diff --git a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
index 6608545ea66f..a4f1fe63659a 100644
--- a/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
+++ b/Documentation/devicetree/bindings/mailbox/arm,mhuv2.yaml
@@ -192,18 +192,17 @@ examples:
arm,mhuv2-protocols = <1 1>, <1 7>, <0 2>;
};
- mhu_client: scb@2e000000 {
- compatible = "fujitsu,mb86s70-scb-1.0";
- reg = <0 0x2e000000 0 0x4000>;
-
- mboxes =
- //data-transfer protocol with 5 windows, mhu-tx
- <&mhu_tx 2 0>,
- //data-transfer protocol with 7 windows, mhu-tx
- <&mhu_tx 3 0>,
- //doorbell protocol channel 4, doorbell 27, mhu-tx
- <&mhu_tx 4 27>,
- //data-transfer protocol with 1 window, mhu-rx
- <&mhu_rx 0 0>;
+ mhu_client: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-dsp";
+ reg = <0 0x596e8000 0 0x88000>;
+ clocks = <&adma_lpcg 0>, <&adma_lpcg 1>, <&adma_lpcg 2>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd 0>, <&pd 1>, <&pd 2>, <&pd 3>;
+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
+ mboxes = <&mhu_tx 2 0>, //data-transfer protocol with 5 windows, mhu-tx
+ <&mhu_tx 3 0>, //data-transfer protocol with 7 windows, mhu-tx
+ <&mhu_rx 2 27>, //doorbell protocol channel 2, doorbell 27, mhu-rx
+ <&mhu_rx 0 0>; //data-transfer protocol with 1 window, mhu-rx
+ memory-region = <&dsp_reserved>;
};
};
diff --git a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt b/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
deleted file mode 100644
index 12371f5c6cd9..000000000000
--- a/Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
+++ /dev/null
@@ -1,184 +0,0 @@
-OMAP2+ and K3 Mailbox
-=====================
-
-The OMAP mailbox hardware facilitates communication between different processors
-using a queued mailbox interrupt mechanism. The IP block is external to the
-various processor subsystems and is connected on an interconnect bus. The
-communication is achieved through a set of registers for message storage and
-interrupt configuration registers.
-
-Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
-interrupt lines. An output interrupt line is routed to an interrupt controller
-within a processor subsystem, and there can be more than one line going to a
-specific processor's interrupt controller. The interrupt line connections are
-fixed for an instance and are dictated by the IP integration into the SoC
-(excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
-programmable through a set of interrupt configuration registers, and have a rx
-and tx interrupt source per h/w fifo. Communication between different processors
-is achieved through the appropriate programming of the rx and tx interrupt
-sources on the appropriate interrupt lines.
-
-The number of h/w fifo queues and interrupt lines dictate the usable registers.
-All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
-instance. DRA7xx has multiple instances with different number of h/w fifo queues
-and interrupt lines between different instances. The interrupt lines can also be
-routed to different processor sub-systems on DRA7xx as they are routed through
-the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
-SoCs has each of these instances form a cluster and combine multiple clusters
-into a single IP block present within the Main NavSS. The interrupt lines from
-all these clusters are multiplexed and routed to different processor subsystems
-over a limited number of common interrupt output lines of an Interrupt Router.
-The AM64x SoCS also uses a single IP block comprising of multiple clusters,
-but the number of clusters are smaller, and the interrupt output lines are
-connected directly to various processors.
-
-Mailbox Device Node:
-====================
-A Mailbox device node is used to represent a Mailbox IP instance/cluster within
-a SoC. The sub-mailboxes are represented as child nodes of this parent node.
-
-Required properties:
---------------------
-- compatible: Should be one of the following,
- "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
- "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
- "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
- AM43xx and DRA7xx SoCs
- "ti,am654-mailbox" for K3 AM65x and J721E SoCs
- "ti,am64-mailbox" for K3 AM64x SoCs
-- reg: Contains the mailbox register address range (base
- address and length)
-- interrupts: Contains the interrupt information for the mailbox
- device. The format is dependent on which interrupt
- controller the Mailbox device uses
-- #mbox-cells: Common mailbox binding property to identify the number
- of cells required for the mailbox specifier. Should be
- 1
-- ti,mbox-num-users: Number of targets (processor devices) that the mailbox
- device can interrupt
-- ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
-
-SoC-specific Required properties:
----------------------------------
-The following are mandatory properties for the OMAP architecture based SoCs
-only:
-- ti,hwmods: Name of the hwmod associated with the mailbox. This
- should be defined in the mailbox node only if the node
- is not defined as a child node of a corresponding sysc
- interconnect node.
-
-The following are mandatory properties for the K3 AM65x and J721E SoCs only:
-- interrupt-parent: Should contain a phandle to the TI-SCI interrupt
- controller node that is used to dynamically program
- the interrupt routes between the IP and the main GIC
- controllers. See the following binding for additional
- details,
- Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
-
-Child Nodes:
-============
-A child node is used for representing the actual sub-mailbox device that is
-used for the communication between the host processor and a remote processor.
-Each child node should have a unique node name across all the different
-mailbox device nodes.
-
-Required properties:
---------------------
-- ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
-- ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
-
-Sub-mailbox Descriptor Data
----------------------------
-Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
-data that represent the following:
- Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
- (ti,mbox-tx) or for receiving (ti,mbox-rx)
- Cell #2 (irq_id) - irq identifier index number to use from the parent's
- interrupts data. Should be 0 for most of the cases, a
- positive index value is seen only on mailboxes that have
- multiple interrupt lines connected to the MPU processor.
- Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
- associated with generating a tx/rx fifo interrupt.
-
-Optional Properties:
---------------------
-- ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
- to send messages without triggering a Tx ready interrupt,
- and to control the Tx ticker. Should be used only on
- sub-mailboxes used to communicate with WkupM3 remote
- processor on AM33xx/AM43xx SoCs.
-
-Mailbox Users:
-==============
-A device needing to communicate with a target processor device should specify
-them using the common mailbox binding properties, "mboxes" and the optional
-"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
-for details). Each value of the mboxes property should contain a phandle to the
-mailbox controller device node and an args specifier that will be the phandle to
-the intended sub-mailbox child node to be used for communication. The equivalent
-"mbox-names" property value can be used to give a name to the communication channel
-to be used by the client user.
-
-
-Example:
---------
-
-1. /* OMAP4 */
-mailbox: mailbox@4a0f4000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x4a0f4000 0x200>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <3>;
- ti,mbox-num-fifos = <8>;
- mbox_ipu: mbox_ipu {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <1 0 0>;
- };
- mbox_dsp: mbox_dsp {
- ti,mbox-tx = <3 0 0>;
- ti,mbox-rx = <2 0 0>;
- };
-};
-
-dsp {
- ...
- mboxes = <&mailbox &mbox_dsp>;
- ...
-};
-
-2. /* AM33xx */
-mailbox: mailbox@480c8000 {
- compatible = "ti,omap4-mailbox";
- reg = <0x480C8000 0x200>;
- interrupts = <77>;
- ti,hwmods = "mailbox";
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <8>;
- mbox_wkupm3: wkup_m3 {
- ti,mbox-tx = <0 0 0>;
- ti,mbox-rx = <0 0 3>;
- };
-};
-
-3. /* AM65x */
-&cbass_main {
- cbass_main_navss: interconnect0 {
- mailbox0_cluster0: mailbox@31f80000 {
- compatible = "ti,am654-mailbox";
- reg = <0x00 0x31f80000 0x00 0x200>;
- #mbox-cells = <1>;
- ti,mbox-num-users = <4>;
- ti,mbox-num-fifos = <16>;
- interrupt-parent = <&intr_main_navss>;
- interrupts = <164 0>;
-
- mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
- ti,mbox-tx = <1 0 0>;
- ti,mbox-rx = <0 0 0>;
- };
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml
index 3b7ab61a144f..b15da9ba90b2 100644
--- a/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/st,stm32-ipcc.yaml
@@ -32,7 +32,6 @@ properties:
- description: tx channel free
- description: wakeup source
minItems: 2
- maxItems: 3
interrupt-names:
items:
@@ -40,7 +39,6 @@ properties:
- const: tx
- const: wakeup
minItems: 2
- maxItems: 3
wakeup-source: true
diff --git a/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
new file mode 100644
index 000000000000..e864d798168d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
@@ -0,0 +1,308 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/ti,omap-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI OMAP2+ and K3 Mailbox devices
+
+maintainers:
+ - Suman Anna <s-anna@ti.com>
+
+description: |
+ The OMAP Mailbox hardware facilitates communication between different
+ processors using a queued mailbox interrupt mechanism. The IP block is
+ external to the various processor subsystems and is connected on an
+ interconnect bus. The communication is achieved through a set of registers
+ for message storage and interrupt configuration registers.
+
+ Each mailbox IP block/cluster has a certain number of h/w fifo queues and
+ output interrupt lines. An output interrupt line is routed to an interrupt
+ controller within a processor subsystem, and there can be more than one line
+ going to a specific processor's interrupt controller. The interrupt line
+ connections are fixed for an instance and are dictated by the IP integration
+ into the SoC (excluding the SoCs that have an Interrupt Crossbar or an
+ Interrupt Router IP). Each interrupt line is programmable through a set of
+ interrupt configuration registers, and have a rx and tx interrupt source per
+ h/w fifo. Communication between different processors is achieved through the
+ appropriate programming of the rx and tx interrupt sources on the appropriate
+ interrupt lines.
+
+ The number of h/w fifo queues and interrupt lines dictate the usable
+ registers. All the current OMAP SoCs except for the newest DRA7xx SoC has a
+ single IP instance. DRA7xx has multiple instances with different number of
+ h/w fifo queues and interrupt lines between different instances. The interrupt
+ lines can also be routed to different processor sub-systems on DRA7xx as they
+ are routed through the Crossbar, a kind of interrupt router/multiplexer. The
+ K3 AM65x, J721E and J7200 SoCs has each of these instances form a cluster and
+ combine multiple clusters into a single IP block present within the Main
+ NavSS. The interrupt lines from all these clusters are multiplexed and routed
+ to different processor subsystems over a limited number of common interrupt
+ output lines of an Interrupt Router. The AM64x SoCS also uses a single IP
+ block comprising of multiple clusters, but the number of clusters are
+ smaller, and the interrupt output lines are connected directly to various
+ processors.
+
+ Mailbox Controller Nodes
+ =========================
+ A Mailbox device node is used to represent a Mailbox IP instance/cluster
+ within a SoC. The sub-mailboxes (actual communication channels) are
+ represented as child nodes of this parent node.
+
+ Mailbox Users
+ ==============
+ A device needing to communicate with a target processor device should specify
+ them using the common mailbox binding properties, "mboxes" and the optional
+ "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
+ for details). Each value of the mboxes property should contain a phandle to
+ the mailbox controller device node and an args specifier that will be the
+ phandle to the intended sub-mailbox child node to be used for communication.
+ The equivalent "mbox-names" property value can be used to give a name to the
+ communication channel to be used by the client user.
+
+$defs:
+ omap-mbox-descriptor:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ The omap-mbox-descriptor is made of up of 3 cells and represents a single
+ uni-directional communication channel. A typical sub-mailbox device uses
+ two such channels - one for transmitting (Tx) and one for receiving (Rx).
+ items:
+ - description:
+ mailbox fifo id used either for transmitting on ti,mbox-tx channel or
+ for receiving on ti,mbox-rx channel (fifo_id). This is the hardware
+ fifo number within a mailbox cluster.
+ - description:
+ irq identifier index number to use from the parent's interrupts data.
+ Should be 0 for most of the cases, a positive index value is seen only
+ on mailboxes that have multiple interrupt lines connected to the MPU
+ processor (irq_id). This is an index number in the listed interrupts
+ property in the DT nodes.
+ - description:
+ mailbox user id for identifying the interrupt line associated with
+ generating a tx/rx fifo interrupt (usr_id). This is the hardware
+ user id number within a mailbox cluster.
+
+ omap-sub-mailbox:
+ type: object
+ description:
+ The omap-sub-mailbox is a child node within a Mailbox controller device
+ node and represents the actual communication channel used to send and
+ receive messages between the host processor and a remote processor. Each
+ child node should have a unique node name across all the different mailbox
+ device nodes.
+
+ properties:
+ ti,mbox-tx:
+ $ref: "#/$defs/omap-mbox-descriptor"
+ description: sub-mailbox descriptor property defining a Tx fifo.
+
+ ti,mbox-rx:
+ $ref: "#/$defs/omap-mbox-descriptor"
+ description: sub-mailbox descriptor property defining a Rx fifo.
+
+ ti,mbox-send-noirq:
+ type: boolean
+ description:
+ Quirk flag to allow the client user of this sub-mailbox to send
+ messages without triggering a Tx ready interrupt, and to control
+ the Tx ticker. Should be used only on sub-mailboxes used to
+ communicate with WkupM3 remote processor on AM33xx/AM43xx SoCs.
+
+ required:
+ - ti,mbox-tx
+ - ti,mbox-rx
+
+properties:
+ compatible:
+ enum:
+ - ti,omap2-mailbox # for OMAP2420, OMAP2430 SoCs
+ - ti,omap3-mailbox # for OMAP3430, OMAP3630 SoCs
+ - ti,omap4-mailbox # for OMAP44xx, OMAP54xx, AM33xx, AM43xx and DRA7xx SoCs
+ - ti,am654-mailbox # for K3 AM65x, J721E and J7200 SoCs
+ - ti,am64-mailbox # for K3 AM64x SoCs
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Contains the interrupt information for the mailbox device. The format is
+ dependent on which interrupt controller the Mailbox device uses. The
+ number of interrupts listed will at most be the value specified in
+ ti,mbox-num-users property, but is usually limited by the number of
+ interrupts reaching the main processor. An interrupt-parent property
+ is required on SoCs where the interrupt lines are connected through a
+ Interrupt Router before reaching the main processor's GIC.
+
+ "#mbox-cells":
+ const: 1
+ description:
+ The specifier is a phandle to an omap-sub-mailbox device.
+
+ ti,mbox-num-users:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Number of targets (processor devices) that the mailbox device can
+ interrupt.
+
+ ti,mbox-num-fifos:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Number of h/w fifo queues within the mailbox IP block.
+
+ ti,hwmods:
+ $ref: /schemas/types.yaml#/definitions/string
+ deprecated: true
+ description:
+ Name of the hwmod associated with the mailbox. This should be defined
+ in the mailbox node only if the node is not defined as a child node of
+ a corresponding sysc interconnect node.
+
+ This property is only needed on some legacy OMAP SoCs which have not
+ yet been converted to the ti,sysc interconnect hierarachy, but is
+ otherwise considered obsolete.
+
+patternProperties:
+ "^mbox-[a-z0-9-]+$":
+ $ref: "#/$defs/omap-sub-mailbox"
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#mbox-cells"
+ - ti,mbox-num-users
+ - ti,mbox-num-fifos
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-mailbox
+ then:
+ required:
+ - interrupt-parent
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-mailbox
+ - ti,am64-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 4
+ ti,mbox-num-fifos:
+ const: 16
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap4-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ enum: [3, 4]
+ ti,mbox-num-fifos:
+ enum: [8, 12]
+ interrupts:
+ minItems: 1
+ maxItems: 4
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap3-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 2
+ ti,mbox-num-fifos:
+ const: 2
+ interrupts:
+ minItems: 1
+ maxItems: 1
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - ti,omap2-mailbox
+ then:
+ properties:
+ ti,mbox-num-users:
+ const: 4
+ ti,mbox-num-fifos:
+ const: 6
+ interrupts:
+ minItems: 1
+ maxItems: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ /* OMAP4 */
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ mailbox: mailbox@4a0f4000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x4a0f4000 0x200>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <3>;
+ ti,mbox-num-fifos = <8>;
+
+ mbox_ipu: mbox-ipu {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <1 0 0>;
+ };
+ mbox_dsp: mbox-dsp {
+ ti,mbox-tx = <3 0 0>;
+ ti,mbox-rx = <2 0 0>;
+ };
+ };
+
+ dsp {
+ mboxes = <&mailbox &mbox_dsp>;
+ };
+
+ - |
+ /* AM33xx */
+ mailbox1: mailbox@480c8000 {
+ compatible = "ti,omap4-mailbox";
+ reg = <0x480c8000 0x200>;
+ interrupts = <77>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <8>;
+
+ mbox_wkupm3: mbox-wkup-m3 {
+ ti,mbox-tx = <0 0 0>;
+ ti,mbox-rx = <0 0 3>;
+ ti,mbox-send-noirq;
+ };
+ };
+
+ - |
+ /* AM65x */
+ mailbox0_cluster0: mailbox@31f80000 {
+ compatible = "ti,am654-mailbox";
+ reg = <0x31f80000 0x200>;
+ #mbox-cells = <1>;
+ ti,mbox-num-users = <4>;
+ ti,mbox-num-fifos = <16>;
+ interrupt-parent = <&intr_main_navss>;
+ interrupts = <436>;
+
+ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
+ ti,mbox-tx = <1 0 0>;
+ ti,mbox-rx = <0 0 0>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
index b902495d278b..5044c4bb94e0 100644
--- a/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
+++ b/Documentation/devicetree/bindings/media/amlogic,gx-vdec.yaml
@@ -67,7 +67,6 @@ properties:
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dos_parser
- const: dos
diff --git a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml b/Documentation/devicetree/bindings/media/i2c/adv7180.yaml
index bcfd93739b4f..3ce4af143a3a 100644
--- a/Documentation/devicetree/bindings/media/i2c/adv7180.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/adv7180.yaml
@@ -36,7 +36,13 @@ properties:
maxItems: 1
port:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
ports: true
diff --git a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adv7604.yaml
index df634b0c1f8c..de15cebe2955 100644
--- a/Documentation/devicetree/bindings/media/i2c/adv7604.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/adv7604.yaml
@@ -30,7 +30,6 @@ properties:
reg-names:
minItems: 1
- maxItems: 13
items:
- const: main
- enum: [ avlink, cec, infoframe, esdp, dpp, afe, rep, edid, hdmi, test, cp, vdp ]
diff --git a/Documentation/devicetree/bindings/media/i2c/imx258.yaml b/Documentation/devicetree/bindings/media/i2c/imx258.yaml
index 515317eff41a..cde0f7383b2a 100644
--- a/Documentation/devicetree/bindings/media/i2c/imx258.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/imx258.yaml
@@ -49,7 +49,7 @@ properties:
# See ../video-interfaces.txt for more details
port:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
index ee16102fdfe7..02f656e78700 100644
--- a/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/maxim,max9286.yaml
@@ -111,17 +111,10 @@ properties:
i2c-mux:
type: object
+ $ref: /schemas/i2c/i2c-mux.yaml#
+ unevaluatedProperties: false
description: |
- Each GMSL link is modelled as a child bus of an i2c bus
- multiplexer/switch, in accordance with bindings described in
- Documentation/devicetree/bindings/i2c/i2c-mux.txt.
-
- properties:
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
+ Each GMSL link is modelled as a child bus of an i2c bus multiplexer/switch.
patternProperties:
"^i2c@[0-3]$":
@@ -133,12 +126,6 @@ properties:
channels.
properties:
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
reg:
description: The index of the GMSL channel.
maxItems: 1
@@ -173,10 +160,6 @@ properties:
additionalProperties: false
- additionalProperties: false
-
- additionalProperties: false
-
required:
- compatible
- reg
diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml
index 9149f5685688..246dc5fec716 100644
--- a/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5648.yaml
@@ -45,7 +45,7 @@ properties:
port:
description: MIPI CSI-2 transmitter port
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml
index 0699c7e4fdeb..b962863e4f65 100644
--- a/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov8865.yaml
@@ -45,7 +45,7 @@ properties:
port:
description: MIPI CSI-2 transmitter port
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
additionalProperties: false
properties:
diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml
index 27cc5b7ff613..f5055b9db693 100644
--- a/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml
+++ b/Documentation/devicetree/bindings/media/i2c/sony,imx334.yaml
@@ -37,7 +37,7 @@ properties:
port:
additionalProperties: false
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
properties:
endpoint:
diff --git a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
index c14c7d827b00..b39b84c5f012 100644
--- a/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
+++ b/Documentation/devicetree/bindings/media/marvell,mmp2-ccic.yaml
@@ -43,7 +43,6 @@ properties:
clocks:
minItems: 1
- maxItems: 3
items:
- description: AXI bus interface clock
- description: Peripheral clock
diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml
index 04013e5dd044..90b4af2c9724 100644
--- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml
@@ -30,7 +30,6 @@ properties:
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml
index 04b9af4db191..177bf81544b1 100644
--- a/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sdm845-venus-v2.yaml
@@ -30,7 +30,6 @@ properties:
power-domain-names:
minItems: 3
- maxItems: 4
items:
- const: venus
- const: vcodec0
diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
index 7b81bd7f2399..ebf8f3d866a5 100644
--- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
+++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml
@@ -30,7 +30,6 @@ properties:
power-domain-names:
minItems: 2
- maxItems: 3
items:
- const: venus
- const: vcodec0
diff --git a/Documentation/devicetree/bindings/media/renesas,drif.yaml b/Documentation/devicetree/bindings/media/renesas,drif.yaml
index 9cd56ff2c316..817a6d566738 100644
--- a/Documentation/devicetree/bindings/media/renesas,drif.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,drif.yaml
@@ -78,7 +78,6 @@ properties:
dma-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: rx
diff --git a/Documentation/devicetree/bindings/media/renesas,vin.yaml b/Documentation/devicetree/bindings/media/renesas,vin.yaml
index 39bb6db2fb32..c0442e79cbb4 100644
--- a/Documentation/devicetree/bindings/media/renesas,vin.yaml
+++ b/Documentation/devicetree/bindings/media/renesas,vin.yaml
@@ -120,7 +120,8 @@ properties:
properties:
port@0:
- $ref: /schemas/graph.yaml#/properties/port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
description:
Input port node, single endpoint describing a parallel input source.
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index a08a32340987..e87e4382807c 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -53,14 +53,12 @@ properties:
apb and smi are mandatory. the async is only for generation 1 smi HW.
gals(global async local sync) also is optional, see below.
minItems: 2
- maxItems: 4
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
- description: smi is the clock for transfer data and command.
- - description: async is asynchronous clock, it help transform the smi
- clock into the emi clock domain.
- - description: gals0 is the path0 clock of gals.
+ - description: Either asynchronous clock to help transform the smi clock
+ into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
- description: gals1 is the path1 clock of gals.
clock-names:
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
index 7ed7839ff0a7..2353f6cf3c80 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
@@ -37,7 +37,6 @@ properties:
description: |
apb and smi are mandatory. gals(global async local sync) is optional.
minItems: 2
- maxItems: 3
items:
- description: apb is Advanced Peripheral Bus clock, It's the clock for
setting the register.
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
deleted file mode 100644
index d2250498c36d..000000000000
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
+++ /dev/null
@@ -1,130 +0,0 @@
-Embedded Memory Controller
-
-Properties:
-- name : Should be emc
-- #address-cells : Should be 1
-- #size-cells : Should be 0
-- compatible : Should contain "nvidia,tegra20-emc".
-- reg : Offset and length of the register set for the device
-- nvidia,use-ram-code : If present, the sub-nodes will be addressed
- and chosen using the ramcode board selector. If omitted, only one
- set of tables can be present and said tables will be used
- irrespective of ram-code configuration.
-- interrupts : Should contain EMC General interrupt.
-- clocks : Should contain EMC clock.
-- nvidia,memory-controller : Phandle of the Memory Controller node.
-- #interconnect-cells : Should be 0.
-- operating-points-v2: See ../bindings/opp/opp.txt for details.
-
-For each opp entry in 'operating-points-v2' table:
-- opp-supported-hw: One bitfield indicating SoC process ID mask
-
- A bitwise AND is performed against this value and if any bit
- matches, the OPP gets enabled.
-
-Optional properties:
-- power-domains: Phandle of the SoC "core" power domain.
-
-Child device nodes describe the memory settings for different configurations and clock rates.
-
-Example:
-
- opp_table: opp-table {
- compatible = "operating-points-v2";
-
- opp@36000000 {
- opp-microvolt = <950000 950000 1300000>;
- opp-hz = /bits/ 64 <36000000>;
- };
- ...
- };
-
- memory-controller@7000f400 {
- #address-cells = < 1 >;
- #size-cells = < 0 >;
- #interconnect-cells = <0>;
- compatible = "nvidia,tegra20-emc";
- reg = <0x7000f400 0x400>;
- interrupts = <0 78 0x04>;
- clocks = <&tegra_car TEGRA20_CLK_EMC>;
- nvidia,memory-controller = <&mc>;
- power-domains = <&domain>;
- operating-points-v2 = <&opp_table>;
- }
-
-
-Embedded Memory Controller ram-code table
-
-If the emc node has the nvidia,use-ram-code property present, then the
-next level of nodes below the emc table are used to specify which settings
-apply for which ram-code settings.
-
-If the emc node lacks the nvidia,use-ram-code property, this level is omitted
-and the tables are stored directly under the emc node (see below).
-
-Properties:
-
-- name : Should be emc-tables
-- nvidia,ram-code : the binary representation of the ram-code board strappings
- for which this node (and children) are valid.
-
-
-
-Embedded Memory Controller configuration table
-
-This is a table containing the EMC register settings for the various
-operating speeds of the memory controller. They are always located as
-subnodes of the emc controller node.
-
-There are two ways of specifying which tables to use:
-
-* The simplest is if there is just one set of tables in the device tree,
- and they will always be used (based on which frequency is used).
- This is the preferred method, especially when firmware can fill in
- this information based on the specific system information and just
- pass it on to the kernel.
-
-* The slightly more complex one is when more than one memory configuration
- might exist on the system. The Tegra20 platform handles this during
- early boot by selecting one out of possible 4 memory settings based
- on a 2-pin "ram code" bootstrap setting on the board. The values of
- these strappings can be read through a register in the SoC, and thus
- used to select which tables to use.
-
-Properties:
-- name : Should be emc-table
-- compatible : Should contain "nvidia,tegra20-emc-table".
-- reg : either an opaque enumerator to tell different tables apart, or
- the valid frequency for which the table should be used (in kHz).
-- clock-frequency : the clock frequency for the EMC at which this
- table should be used (in kHz).
-- nvidia,emc-registers : a 46 word array of EMC registers to be programmed
- for operation at the 'clock-frequency' setting.
- The order and contents of the registers are:
- RC, RFC, RAS, RP, R2W, W2R, R2P, W2P, RD_RCD, WR_RCD, RRD, REXT,
- WDV, QUSE, QRST, QSAFE, RDV, REFRESH, BURST_REFRESH_NUM, PDEX2WR,
- PDEX2RD, PCHG2PDEN, ACT2PDEN, AR2PDEN, RW2PDEN, TXSR, TCKE, TFAW,
- TRPAB, TCLKSTABLE, TCLKSTOP, TREFBW, QUSE_EXTRA, FBIO_CFG6, ODT_WRITE,
- ODT_READ, FBIO_CFG5, CFG_DIG_DLL, DLL_XFORM_DQS, DLL_XFORM_QUSE,
- ZCAL_REF_CNT, ZCAL_WAIT_CNT, AUTO_CAL_INTERVAL, CFG_CLKTRIM_0,
- CFG_CLKTRIM_1, CFG_CLKTRIM_2
-
- emc-table@166000 {
- reg = <166000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = < 166000 >;
- nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 >;
- };
-
- emc-table@333000 {
- reg = <333000>;
- compatible = "nvidia,tegra20-emc-table";
- clock-frequency = < 333000 >;
- nvidia,emc-registers = < 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 0 0 0 0 0 0 0 0 0 0
- 0 0 0 0 >;
- };
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
new file mode 100644
index 000000000000..cac6842dc8f1
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml
@@ -0,0 +1,230 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NVIDIA Tegra20 SoC External Memory Controller
+
+maintainers:
+ - Dmitry Osipenko <digetx@gmail.com>
+ - Jon Hunter <jonathanh@nvidia.com>
+ - Thierry Reding <thierry.reding@gmail.com>
+
+description: |
+ The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
+ service the request stream sent from Memory Controller. The EMC also has
+ various performance-affecting settings beyond the obvious SDRAM configuration
+ parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
+ standard protocols: DDR1, LPDDR2 and DDR2.
+
+properties:
+ compatible:
+ const: nvidia,tegra20-emc
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ "#interconnect-cells":
+ const: 0
+
+ nvidia,memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of the Memory Controller node.
+
+ power-domains:
+ maxItems: 1
+ description:
+ Phandle of the SoC "core" power domain.
+
+ operating-points-v2:
+ description:
+ Should contain freqs and voltages and opp-supported-hw property, which
+ is a bitfield indicating SoC process ID mask.
+
+ nvidia,use-ram-code:
+ type: boolean
+ description:
+ If present, the emc-tables@ sub-nodes will be addressed.
+
+$defs:
+ emc-table:
+ type: object
+ properties:
+ compatible:
+ const: nvidia,tegra20-emc-table
+
+ clock-frequency:
+ description:
+ Memory clock rate in kHz.
+ minimum: 1000
+ maximum: 900000
+
+ reg:
+ maxItems: 1
+ description:
+ Either an opaque enumerator to tell different tables apart, or
+ the valid frequency for which the table should be used (in kHz).
+
+ nvidia,emc-registers:
+ description:
+ EMC timing characterization data. These are the registers
+ (see section "15.4.1 EMC Registers" in the TRM) whose values
+ need to be specified, according to the board documentation.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ - description: EMC_RC
+ - description: EMC_RFC
+ - description: EMC_RAS
+ - description: EMC_RP
+ - description: EMC_R2W
+ - description: EMC_W2R
+ - description: EMC_R2P
+ - description: EMC_W2P
+ - description: EMC_RD_RCD
+ - description: EMC_WR_RCD
+ - description: EMC_RRD
+ - description: EMC_REXT
+ - description: EMC_WDV
+ - description: EMC_QUSE
+ - description: EMC_QRST
+ - description: EMC_QSAFE
+ - description: EMC_RDV
+ - description: EMC_REFRESH
+ - description: EMC_BURST_REFRESH_NUM
+ - description: EMC_PDEX2WR
+ - description: EMC_PDEX2RD
+ - description: EMC_PCHG2PDEN
+ - description: EMC_ACT2PDEN
+ - description: EMC_AR2PDEN
+ - description: EMC_RW2PDEN
+ - description: EMC_TXSR
+ - description: EMC_TCKE
+ - description: EMC_TFAW
+ - description: EMC_TRPAB
+ - description: EMC_TCLKSTABLE
+ - description: EMC_TCLKSTOP
+ - description: EMC_TREFBW
+ - description: EMC_QUSE_EXTRA
+ - description: EMC_FBIO_CFG6
+ - description: EMC_ODT_WRITE
+ - description: EMC_ODT_READ
+ - description: EMC_FBIO_CFG5
+ - description: EMC_CFG_DIG_DLL
+ - description: EMC_DLL_XFORM_DQS
+ - description: EMC_DLL_XFORM_QUSE
+ - description: EMC_ZCAL_REF_CNT
+ - description: EMC_ZCAL_WAIT_CNT
+ - description: EMC_AUTO_CAL_INTERVAL
+ - description: EMC_CFG_CLKTRIM_0
+ - description: EMC_CFG_CLKTRIM_1
+ - description: EMC_CFG_CLKTRIM_2
+
+ required:
+ - clock-frequency
+ - compatible
+ - reg
+ - nvidia,emc-registers
+
+ additionalProperties: false
+
+patternProperties:
+ "^emc-table@[0-9]+$":
+ $ref: "#/$defs/emc-table"
+
+ "^emc-tables@[a-z0-9-]+$":
+ type: object
+ properties:
+ reg:
+ maxItems: 1
+ description:
+ An opaque enumerator to tell different tables apart.
+
+ nvidia,ram-code:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Value of RAM_CODE this timing set is used for.
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ patternProperties:
+ "^emc-table@[0-9]+$":
+ $ref: "#/$defs/emc-table"
+
+ required:
+ - nvidia,ram-code
+
+ additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - nvidia,memory-controller
+ - "#interconnect-cells"
+ - operating-points-v2
+
+additionalProperties: false
+
+examples:
+ - |
+ external-memory-controller@7000f400 {
+ compatible = "nvidia,tegra20-emc";
+ reg = <0x7000f400 0x400>;
+ interrupts = <0 78 4>;
+ clocks = <&clock_controller 57>;
+
+ nvidia,memory-controller = <&mc>;
+ operating-points-v2 = <&dvfs_opp_table>;
+ power-domains = <&domain>;
+
+ #interconnect-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nvidia,use-ram-code;
+
+ emc-tables@0 {
+ nvidia,ram-code = <0>;
+ reg = <0>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
index b52e7a33f0f9..190230216de8 100644
--- a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
+++ b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
@@ -16,8 +16,8 @@ Optional subnodes:
The sub-functions of CPCAP get their own node with their own compatible values,
which are described in the following files:
-- Documentation/devicetree/bindings/power/supply/cpcap-battery.txt
-- Documentation/devicetree/bindings/power/supply/cpcap-charger.txt
+- Documentation/devicetree/bindings/power/supply/cpcap-battery.yaml
+- Documentation/devicetree/bindings/power/supply/cpcap-charger.yaml
- Documentation/devicetree/bindings/regulator/cpcap-regulator.txt
- Documentation/devicetree/bindings/phy/phy-cpcap-usb.txt
- Documentation/devicetree/bindings/input/cpcap-pwrbutton.txt
diff --git a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
index 19fcf59fd2fe..272832e9f8f2 100644
--- a/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
+++ b/Documentation/devicetree/bindings/mfd/ti,j721e-system-controller.yaml
@@ -43,12 +43,10 @@ properties:
patternProperties:
# Optional children
- "^serdes-ln-ctrl@[0-9a-f]+$":
+ "^mux-controller@[0-9a-f]+$":
type: object
- description: |
- This is the SERDES lane control mux. It should follow the bindings
- specified in
- Documentation/devicetree/bindings/mux/reg-mux.txt
+ description:
+ This is the SERDES lane control mux.
required:
- compatible
@@ -68,9 +66,18 @@ examples:
#size-cells = <1>;
ranges;
- serdes_ln_ctrl: serdes-ln-ctrl@4080 {
+ serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
reg = <0x00004080 0x50>;
+
+ #mux-control-cells = <1>;
+ mux-reg-masks =
+ <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
};
};
...
diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
index e75b3a8ba816..4f62ad6ce50c 100644
--- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
@@ -64,7 +64,6 @@ properties:
clocks:
minItems: 2
- maxItems: 4
items:
- description: Bus Clock
- description: Module Clock
@@ -73,7 +72,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 4
items:
- const: ahb
- const: mmc
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
index 369471814496..b5baf439fbac 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml
@@ -116,7 +116,6 @@ properties:
pinctrl-names:
minItems: 1
- maxItems: 4
items:
- const: default
- const: state_100mhz
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 8648d48dbbfd..4e553fd0349f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -38,7 +38,6 @@ properties:
description:
Should contain phandle for the clock feeding the MMC controller.
minItems: 2
- maxItems: 8
items:
- description: source clock (required).
- description: HCLK which used for host (required).
@@ -51,7 +50,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 8
items:
- const: source
- const: hclk
diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
index 1118b6fa93c9..677989bc5924 100644
--- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
+++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml
@@ -75,7 +75,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: core
- const: cd
@@ -107,7 +106,6 @@ properties:
pinctrl-names:
minItems: 1
- maxItems: 2
items:
- const: default
- const: state_uhs
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
index 29399e88ac53..224303f5b913 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
@@ -44,7 +44,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: clk_ahb
- const: clk_xin
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
index aa12480648a5..1c87f4218e18 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
+++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml
@@ -57,7 +57,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: io
- const: core
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index 4a9145ef15d6..57d077c0b7c1 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -25,10 +25,10 @@ The following are mandatory properties for 66AK2G SoCs only:
- power-domains:Should contain a phandle to a PM domain provider node
and an args specifier containing the MMC device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
- clocks: Must contain an entry for each entry in clock-names. Should
be defined as per the he appropriate clock bindings consumer
- usage in Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ usage in Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
- clock-names: Shall be "fck" for the functional clock,
and "mmchsdb_fck" for the debounce clock.
diff --git a/Documentation/devicetree/bindings/mtd/arm-versatile.txt b/Documentation/devicetree/bindings/mtd/arm-versatile.txt
deleted file mode 100644
index 4ec28796a3c0..000000000000
--- a/Documentation/devicetree/bindings/mtd/arm-versatile.txt
+++ /dev/null
@@ -1,26 +0,0 @@
-Flash device on ARM Versatile board
-
-These flash chips are found in the ARM reference designs like Integrator,
-Versatile, RealView, Versatile Express etc.
-
-They are regular CFI compatible (Intel or AMD extended) flash chips with
-some special write protect/VPP bits that can be controlled by the machine's
-system controller.
-
-Required properties:
-- compatible : must be "arm,versatile-flash", "cfi-flash";
-- reg : memory address for the flash chip
-- bank-width : width in bytes of flash interface.
-
-For the rest of the properties, see mtd-physmap.txt.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-flash@34000000 {
- compatible = "arm,versatile-flash", "cfi-flash";
- reg = <0x34000000 0x4000000>;
- bank-width = <4>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt
index 3fa1b34d69ad..efa5b2aba829 100644
--- a/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt
+++ b/Documentation/devicetree/bindings/mtd/cortina,gemini-flash.txt
@@ -9,7 +9,7 @@ Required properties:
- syscon : must be a phandle to the system controller
- bank-width : width in bytes of flash interface, should be <2>
-For the rest of the properties, see mtd-physmap.txt.
+For the rest of the properties, see mtd-physmap.yaml.
The device tree may optionally contain sub-nodes describing partitions of the
address space. See partition.txt for more detail.
diff --git a/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt b/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
deleted file mode 100644
index ad42f4db32f1..000000000000
--- a/Documentation/devicetree/bindings/mtd/cypress,hyperflash.txt
+++ /dev/null
@@ -1,13 +0,0 @@
-Bindings for HyperFlash NOR flash chips compliant with Cypress HyperBus
-specification and supports Cypress CFI specification 1.5 command set.
-
-Required properties:
-- compatible : "cypress,hyperflash", "cfi-flash" for HyperFlash NOR chips
-- reg : Address of flash's memory map
-
-Example:
-
- flash@0 {
- compatible = "cypress,hyperflash", "cfi-flash";
- reg = <0x0 0x4000000>;
- };
diff --git a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt b/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt
deleted file mode 100644
index 4bdcb92ae381..000000000000
--- a/Documentation/devicetree/bindings/mtd/intel,ixp4xx-flash.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Flash device on Intel IXP4xx SoC
-
-This flash is regular CFI compatible (Intel or AMD extended) flash chips with
-specific big-endian or mixed-endian memory access pattern.
-
-Required properties:
-- compatible : must be "intel,ixp4xx-flash", "cfi-flash";
-- reg : memory address for the flash chip
-- bank-width : width in bytes of flash interface, should be <2>
-
-For the rest of the properties, see mtd-physmap.txt.
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
-flash@50000000 {
- compatible = "intel,ixp4xx-flash", "cfi-flash";
- reg = <0x50000000 0x01000000>;
- bank-width = <2>;
-};
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt b/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
deleted file mode 100644
index c69f4f065d23..000000000000
--- a/Documentation/devicetree/bindings/mtd/mtd-physmap.txt
+++ /dev/null
@@ -1,114 +0,0 @@
-CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
-
-Flash chips (Memory Technology Devices) are often used for solid state
-file systems on embedded devices.
-
- - compatible : should contain the specific model of mtd chip(s)
- used, if known, followed by either "cfi-flash", "jedec-flash",
- "mtd-ram" or "mtd-rom".
- - reg : Address range(s) of the mtd chip(s)
- It's possible to (optionally) define multiple "reg" tuples so that
- non-identical chips can be described in one node.
- - bank-width : Width (in bytes) of the bank. Equal to the
- device width times the number of interleaved chips.
- - device-width : (optional) Width of a single mtd chip. If
- omitted, assumed to be equal to 'bank-width'.
- - #address-cells, #size-cells : Must be present if the device has
- sub-nodes representing partitions (see below). In this case
- both #address-cells and #size-cells must be equal to 1.
- - no-unaligned-direct-access: boolean to disable the default direct
- mapping of the flash.
- On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause
- problems with JFFS2 usage, as the local bus (LPB) doesn't support
- unaligned accesses as implemented in the JFFS2 code via memcpy().
- By defining "no-unaligned-direct-access", the flash will not be
- exposed directly to the MTD users (e.g. JFFS2) any more.
- - linux,mtd-name: allow to specify the mtd name for retro capability with
- physmap-flash drivers as boot loader pass the mtd partition via the old
- device name physmap-flash.
- - use-advanced-sector-protection: boolean to enable support for the
- advanced sector protection (Spansion: PPB - Persistent Protection
- Bits) locking.
- - addr-gpios : (optional) List of GPIO descriptors that will be used to
- address the MSBs address lines. The order goes from LSB to MSB.
-
-For JEDEC compatible devices, the following additional properties
-are defined:
-
- - vendor-id : Contains the flash chip's vendor id (1 byte).
- - device-id : Contains the flash chip's device id (1 byte).
-
-For ROM compatible devices (and ROM fallback from cfi-flash), the following
-additional (optional) property is defined:
-
- - erase-size : The chip's physical erase block size in bytes.
-
- The device tree may optionally contain endianness property.
- little-endian or big-endian : It Represents the endianness that should be used
- by the controller to properly read/write data
- from/to the flash. If this property is missing,
- the endianness is chosen by the system
- (potentially based on extra configuration options).
-
-The device tree may optionally contain sub-nodes describing partitions of the
-address space. See partition.txt for more detail.
-
-Example:
-
- flash@ff000000 {
- compatible = "amd,am29lv128ml", "cfi-flash";
- reg = <ff000000 01000000>;
- bank-width = <4>;
- device-width = <1>;
- #address-cells = <1>;
- #size-cells = <1>;
- fs@0 {
- label = "fs";
- reg = <0 f80000>;
- };
- firmware@f80000 {
- label ="firmware";
- reg = <f80000 80000>;
- read-only;
- };
- };
-
-Here an example with multiple "reg" tuples:
-
- flash@f0000000,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "intel,PC48F4400P0VB", "cfi-flash";
- reg = <0 0x00000000 0x02000000
- 0 0x02000000 0x02000000>;
- bank-width = <2>;
- partition@0 {
- label = "test-part1";
- reg = <0 0x04000000>;
- };
- };
-
-An example using SRAM:
-
- sram@2,0 {
- compatible = "samsung,k6f1616u6a", "mtd-ram";
- reg = <2 0 0x00200000>;
- bank-width = <2>;
- };
-
-An example using gpio-addrs
-
- flash@20000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "cfi-flash", "jedec-flash";
- reg = <0x20000000 0x02000000>;
- ranges = <0 0x00000000 0x02000000
- 1 0x02000000 0x02000000>;
- bank-width = <2>;
- addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
- partition@0 {
- label = "test-part1";
- reg = <0 0x04000000>;
- };
- };
diff --git a/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
new file mode 100644
index 000000000000..13c29cc91b59
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description: |
+ Flash chips (Memory Technology Devices) are often used for solid state
+ file systems on embedded devices.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - amd,s29gl01gp
+ - amd,s29gl032a
+ - amd,s29gl256n
+ - amd,s29gl512n
+ - arm,versatile-flash
+ - cortina,gemini-flash
+ - cypress,hyperflash
+ - ge,imp3a-firmware-mirror
+ - ge,imp3a-paged-flash
+ - gef,ppc9a-firmware-mirror
+ - gef,ppc9a-paged-flash
+ - gef,sbc310-firmware-mirror
+ - gef,sbc310-paged-flash
+ - gef,sbc610-firmware-mirror
+ - gef,sbc610-paged-flash
+ - intel,28f128j3
+ - intel,dt28f160
+ - intel,ixp4xx-flash
+ - intel,JS28F128
+ - intel,JS28F640
+ - intel,PC28F640P30T85
+ - numonyx,js28f00a
+ - numonyx,js28f128
+ - sst,sst39vf320
+ - xlnx,xps-mch-emc-2.00.a
+ - const: cfi-flash
+ - items:
+ - enum:
+ - cypress,cy7c1019dv33-10zsxi
+ - arm,vexpress-psram
+ - const: mtd-ram
+ - enum:
+ - cfi-flash
+ - jedec-flash
+ - mtd-ram
+ - mtd-rom
+
+ reg:
+ description: |
+ It's possible to (optionally) define multiple "reg" tuples so that
+ non-identical chips can be described in one node.
+ minItems: 1
+ maxItems: 8
+
+ bank-width:
+ description: Width (in bytes) of the bank. Equal to the device width times
+ the number of interleaved chips.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2, 4 ]
+
+ device-width:
+ description:
+ Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [ 1, 2 ]
+
+ no-unaligned-direct-access:
+ type: boolean
+ description: |
+ Disables the default direct mapping of the flash.
+
+ On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
+ with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
+ accesses as implemented in the JFFS2 code via memcpy(). By defining
+ "no-unaligned-direct-access", the flash will not be exposed directly to
+ the MTD users (e.g. JFFS2) any more.
+
+ linux,mtd-name:
+ description:
+ Allows specifying the mtd name for retro capability with physmap-flash
+ drivers as boot loader pass the mtd partition via the old device name
+ physmap-flash.
+ $ref: /schemas/types.yaml#/definitions/string
+
+ use-advanced-sector-protection:
+ type: boolean
+ description: |
+ Enables support for the advanced sector protection (Spansion: PPB -
+ Persistent Protection Bits) locking.
+
+ erase-size:
+ description: The chip's physical erase block size in bytes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ addr-gpios:
+ description:
+ List of GPIO descriptors that will be used to address the MSBs address
+ lines. The order goes from LSB to MSB.
+ minItems: 1
+ maxItems: 8
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ big-endian: true
+ little-endian: true
+
+patternProperties:
+ '@[0-9a-f]+$':
+ $ref: partitions/partition.yaml
+
+required:
+ - compatible
+ - reg
+
+# FIXME: A parent bus may define timing properties
+additionalProperties: true
+
+examples:
+ - |
+
+ flash@ff000000 {
+ compatible = "cfi-flash";
+ reg = <0xff000000 0x01000000>;
+ bank-width = <4>;
+ device-width = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xff000000 0x01000000>;
+
+ fs@0 {
+ label = "fs";
+ reg = <0 0xf80000>;
+ };
+ firmware@f80000 {
+ label ="firmware";
+ reg = <0xf80000 0x80000>;
+ read-only;
+ };
+ };
+
+ - |
+ /* An example with multiple "reg" tuples */
+
+ flash@0 {
+ compatible = "intel,PC28F640P30T85", "cfi-flash";
+ reg = <0x00000000 0x02000000>,
+ <0x02000000 0x02000000>;
+ bank-width = <2>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x04000000>;
+
+ partition@0 {
+ label = "test-part1";
+ reg = <0 0x04000000>;
+ };
+ };
+
+ - |
+ /* An example using SRAM */
+ bus {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ sram@2,0 {
+ compatible = "mtd-ram";
+ reg = <2 0 0x00200000>;
+ bank-width = <2>;
+ };
+ };
+
+ - |
+ /* An example using addr-gpios */
+ #include <dt-bindings/gpio/gpio.h>
+
+ flash@20000000 {
+ compatible = "cfi-flash";
+ reg = <0x20000000 0x02000000>;
+ bank-width = <2>;
+ addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00000000 0x02000000>,
+ <1 0x02000000 0x02000000>;
+
+ partition@0 {
+ label = "test-part1";
+ reg = <0 0x04000000>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
index faa81c2e5da6..ccfd37b8a0ad 100644
--- a/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
+++ b/Documentation/devicetree/bindings/mtd/ti,am654-hbmc.txt
@@ -13,7 +13,7 @@ Optional properties:
- mux-controls : phandle to the multiplexer that controls selection of
HBMC vs OSPI inside Flash SubSystem (FSS). Default is OSPI,
if property is absent.
- See Documentation/devicetree/bindings/mux/reg-mux.txt
+ See Documentation/devicetree/bindings/mux/reg-mux.yaml
for mmio-mux binding details
Example:
diff --git a/Documentation/devicetree/bindings/mux/adi,adg792a.txt b/Documentation/devicetree/bindings/mux/adi,adg792a.txt
index 96b787a69f50..b0e5bf6903d8 100644
--- a/Documentation/devicetree/bindings/mux/adi,adg792a.txt
+++ b/Documentation/devicetree/bindings/mux/adi,adg792a.txt
@@ -5,7 +5,7 @@ Required properties:
- #mux-control-cells : <0> if parallel (the three muxes are bound together
with a single mux controller controlling all three muxes), or <1> if
not (one mux controller for each mux).
-* Standard mux-controller bindings as described in mux-controller.txt
+* Standard mux-controller bindings as described in mux-controller.yaml
Optional properties for ADG792G:
- gpio-controller : if present, #gpio-cells below is required.
diff --git a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt b/Documentation/devicetree/bindings/mux/adi,adgs1408.txt
index be6947f4d86b..453a38961c13 100644
--- a/Documentation/devicetree/bindings/mux/adi,adgs1408.txt
+++ b/Documentation/devicetree/bindings/mux/adi,adgs1408.txt
@@ -4,7 +4,7 @@ Required properties:
- compatible : Should be one of
* "adi,adgs1408"
* "adi,adgs1409"
-* Standard mux-controller bindings as described in mux-controller.txt
+* Standard mux-controller bindings as described in mux-controller.yaml
Optional properties for ADGS1408/1409:
- gpio-controller : if present, #gpio-cells is required.
diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.txt b/Documentation/devicetree/bindings/mux/gpio-mux.txt
deleted file mode 100644
index b8f746344d80..000000000000
--- a/Documentation/devicetree/bindings/mux/gpio-mux.txt
+++ /dev/null
@@ -1,69 +0,0 @@
-GPIO-based multiplexer controller bindings
-
-Define what GPIO pins are used to control a multiplexer. Or several
-multiplexers, if the same pins control more than one multiplexer.
-
-Required properties:
-- compatible : "gpio-mux"
-- mux-gpios : list of gpios used to control the multiplexer, least
- significant bit first.
-- #mux-control-cells : <0>
-* Standard mux-controller bindings as decribed in mux-controller.txt
-
-Optional properties:
-- idle-state : if present, the state the mux will have when idle. The
- special state MUX_IDLE_AS_IS is the default.
-
-The multiplexer state is defined as the number represented by the
-multiplexer GPIO pins, where the first pin is the least significant
-bit. An active pin is a binary 1, an inactive pin is a binary 0.
-
-Example:
-
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync-1", "in", "out", "sync-2";
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- /* ... */
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- /* ... */
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/mux/gpio-mux.yaml b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
new file mode 100644
index 000000000000..0a7c8d64981a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mux/gpio-mux.yaml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: GPIO-based multiplexer controller bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ Define what GPIO pins are used to control a multiplexer. Or several
+ multiplexers, if the same pins control more than one multiplexer.
+
+ The multiplexer state is defined as the number represented by the
+ multiplexer GPIO pins, where the first pin is the least significant
+ bit. An active pin is a binary 1, an inactive pin is a binary 0.
+
+properties:
+ compatible:
+ const: gpio-mux
+
+ mux-gpios:
+ description:
+ List of gpios used to control the multiplexer, least significant bit first.
+
+ '#mux-control-cells':
+ const: 0
+
+ idle-state:
+ default: -1
+
+required:
+ - compatible
+ - mux-gpios
+ - "#mux-control-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ reg = <0x3c>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mux/mux-consumer.yaml b/Documentation/devicetree/bindings/mux/mux-consumer.yaml
new file mode 100644
index 000000000000..7af93298ab5c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mux/mux-consumer.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common multiplexer controller consumer bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ Mux controller consumers should specify a list of mux controllers that they
+ want to use with a property containing a 'mux-ctrl-list':
+
+ mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
+ single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
+ mux-ctrl-phandle : phandle to mux controller node
+ mux-ctrl-specifier : array of #mux-control-cells specifying the
+ given mux controller (controller specific)
+
+ Mux controller properties should be named "mux-controls". The exact meaning of
+ each mux controller property must be documented in the device tree binding for
+ each consumer. An optional property "mux-control-names" may contain a list of
+ strings to label each of the mux controllers listed in the "mux-controls"
+ property.
+
+ mux-ctrl-specifier typically encodes the chip-relative mux controller number.
+ If the mux controller chip only provides a single mux controller, the
+ mux-ctrl-specifier can typically be left out.
+
+select: true
+
+properties:
+ mux-controls:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+
+ mux-control-names:
+ description:
+ Devices that use more than a single mux controller can use the
+ "mux-control-names" property to map the name of the requested mux
+ controller to an index into the list given by the "mux-controls" property.
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/mux/mux-controller.txt b/Documentation/devicetree/bindings/mux/mux-controller.txt
deleted file mode 100644
index 4f47e4bd2fa0..000000000000
--- a/Documentation/devicetree/bindings/mux/mux-controller.txt
+++ /dev/null
@@ -1,157 +0,0 @@
-Common multiplexer controller bindings
-======================================
-
-A multiplexer (or mux) controller will have one, or several, consumer devices
-that uses the mux controller. Thus, a mux controller can possibly control
-several parallel multiplexers. Presumably there will be at least one
-multiplexer needed by each consumer, but a single mux controller can of course
-control several multiplexers for a single consumer.
-
-A mux controller provides a number of states to its consumers, and the state
-space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
-0-7 for an 8-way multiplexer, etc.
-
-
-Consumers
----------
-
-Mux controller consumers should specify a list of mux controllers that they
-want to use with a property containing a 'mux-ctrl-list':
-
- mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
- single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
- mux-ctrl-phandle : phandle to mux controller node
- mux-ctrl-specifier : array of #mux-control-cells specifying the
- given mux controller (controller specific)
-
-Mux controller properties should be named "mux-controls". The exact meaning of
-each mux controller property must be documented in the device tree binding for
-each consumer. An optional property "mux-control-names" may contain a list of
-strings to label each of the mux controllers listed in the "mux-controls"
-property.
-
-Drivers for devices that use more than a single mux controller can use the
-"mux-control-names" property to map the name of the requested mux controller
-to an index into the list given by the "mux-controls" property.
-
-mux-ctrl-specifier typically encodes the chip-relative mux controller number.
-If the mux controller chip only provides a single mux controller, the
-mux-ctrl-specifier can typically be left out.
-
-Example:
-
- /* One consumer of a 2-way mux controller (one GPIO-line) */
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
- mux-control-names = "adc";
-
- channels = "sync", "in";
- };
-
-Note that in the example above, specifying the "mux-control-names" is redundant
-because there is only one mux controller in the list. However, if the driver
-for the consumer node in fact asks for a named mux controller, that name is of
-course still required.
-
- /*
- * Two consumers (one for an ADC line and one for an i2c bus) of
- * parallel 4-way multiplexers controlled by the same two GPIO-lines.
- */
- mux: mux-controller {
- compatible = "gpio-mux";
- #mux-control-cells = <0>;
-
- mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
- <&pioA 1 GPIO_ACTIVE_HIGH>;
- };
-
- adc-mux {
- compatible = "io-channel-mux";
- io-channels = <&adc 0>;
- io-channel-names = "parent";
-
- mux-controls = <&mux>;
-
- channels = "sync-1", "in", "out", "sync-2";
- };
-
- i2c-mux {
- compatible = "i2c-mux";
- i2c-parent = <&i2c1>;
-
- mux-controls = <&mux>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- i2c@0 {
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ssd1307: oled@3c {
- /* ... */
- };
- };
-
- i2c@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- pca9555: pca9555@20 {
- /* ... */
- };
- };
- };
-
-
-Mux controller nodes
---------------------
-
-Mux controller nodes must specify the number of cells used for the
-specifier using the '#mux-control-cells' property.
-
-Optionally, mux controller nodes can also specify the state the mux should
-have when it is idle. The idle-state property is used for this. If the
-idle-state is not present, the mux controller is typically left as is when
-it is idle. For multiplexer chips that expose several mux controllers, the
-idle-state property is an array with one idle state for each mux controller.
-
-The special value (-1) may be used to indicate that the mux should be left
-as is when it is idle. This is the default, but can still be useful for
-mux controller chips with more than one mux controller, particularly when
-there is a need to "step past" a mux controller and set some other idle
-state for a mux controller with a higher index.
-
-Some mux controllers have the ability to disconnect the input/output of the
-multiplexer. Using this disconnected high-impedance state as the idle state
-is indicated with idle state (-2).
-
-These constants are available in
-
- #include <dt-bindings/mux/mux.h>
-
-as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).
-
-An example mux controller node look like this (the adg972a chip is a triple
-4-way multiplexer):
-
- mux: mux-controller@50 {
- compatible = "adi,adg792a";
- reg = <0x50>;
- #mux-control-cells = <1>;
-
- idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
- };
diff --git a/Documentation/devicetree/bindings/mux/mux-controller.yaml b/Documentation/devicetree/bindings/mux/mux-controller.yaml
new file mode 100644
index 000000000000..736a84c3b6a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/mux/mux-controller.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/mux-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common multiplexer controller provider bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |
+ A multiplexer (or mux) controller will have one, or several, consumer devices
+ that uses the mux controller. Thus, a mux controller can possibly control
+ several parallel multiplexers. Presumably there will be at least one
+ multiplexer needed by each consumer, but a single mux controller can of course
+ control several multiplexers for a single consumer.
+
+ A mux controller provides a number of states to its consumers, and the state
+ space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
+ 0-7 for an 8-way multiplexer, etc.
+
+
+ Mux controller nodes
+ --------------------
+
+ Mux controller nodes must specify the number of cells used for the
+ specifier using the '#mux-control-cells' property.
+
+ Optionally, mux controller nodes can also specify the state the mux should
+ have when it is idle. The idle-state property is used for this. If the
+ idle-state is not present, the mux controller is typically left as is when
+ it is idle. For multiplexer chips that expose several mux controllers, the
+ idle-state property is an array with one idle state for each mux controller.
+
+ The special value (-1) may be used to indicate that the mux should be left
+ as is when it is idle. This is the default, but can still be useful for
+ mux controller chips with more than one mux controller, particularly when
+ there is a need to "step past" a mux controller and set some other idle
+ state for a mux controller with a higher index.
+
+ Some mux controllers have the ability to disconnect the input/output of the
+ multiplexer. Using this disconnected high-impedance state as the idle state
+ is indicated with idle state (-2).
+
+ These constants are available in
+
+ #include <dt-bindings/mux/mux.h>
+
+ as MUX_IDLE_AS_IS (-1) and MUX_IDLE_DISCONNECT (-2).
+
+ An example mux controller node look like this (the adg972a chip is a triple
+ 4-way multiplexer):
+
+ mux: mux-controller@50 {
+ compatible = "adi,adg792a";
+ reg = <0x50>;
+ #mux-control-cells = <1>;
+
+ idle-state = <MUX_IDLE_DISCONNECT MUX_IDLE_AS_IS 2>;
+ };
+
+select:
+ anyOf:
+ - properties:
+ $nodename:
+ pattern: '^mux-controller'
+ - required:
+ - '#mux-control-cells'
+
+properties:
+ $nodename:
+ pattern: '^mux-controller(@.*|-[0-9a-f]+)?$'
+
+ '#mux-control-cells':
+ enum: [ 0, 1 ]
+
+ idle-state:
+ $ref: /schemas/types.yaml#/definitions/int32
+ minimum: -2
+
+ idle-states:
+ description: |
+ Mux controller nodes can specify the state the mux should have when it is
+ idle. If the idle-state is not present, the mux controller is typically
+ left as is when it is idle. For multiplexer chips that expose several mux
+ controllers, the idle-state property is an array with one idle state for
+ each mux controller.
+
+ The special value (-1) may be used to indicate that the mux should be left
+ as is when it is idle. This is the default, but can still be useful for
+ mux controller chips with more than one mux controller, particularly when
+ there is a need to "step past" a mux controller and set some other idle
+ state for a mux controller with a higher index.
+
+ Some mux controllers have the ability to disconnect the input/output of the
+ multiplexer. Using this disconnected high-impedance state as the idle state
+ is indicated with idle state (-2).
+ $ref: /schemas/types.yaml#/definitions/int32-array
+ items:
+ minimum: -2
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /* One consumer of a 2-way mux controller (one GPIO-line) */
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux>;
+ mux-control-names = "adc";
+
+ channels = "sync", "in";
+ };
+
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ /*
+ * Two consumers (one for an ADC line and one for an i2c bus) of
+ * parallel 4-way multiplexers controlled by the same two GPIO-lines.
+ */
+ mux2: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
+ <&pioA 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ adc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 0>;
+ io-channel-names = "parent";
+
+ mux-controls = <&mux2>;
+
+ channels = "sync-1", "in", "out", "sync-2";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ i2c-parent = <&i2c1>;
+
+ mux-controls = <&mux2>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ssd1307: oled@3c {
+ reg = <0x3c>;
+ };
+ };
+
+ i2c@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pca9555: pca9555@20 {
+ reg = <0x20>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/mux/reg-mux.txt b/Documentation/devicetree/bindings/mux/reg-mux.txt
deleted file mode 100644
index 4afd7ba73d60..000000000000
--- a/Documentation/devicetree/bindings/mux/reg-mux.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-Generic register bitfield-based multiplexer controller bindings
-
-Define register bitfields to be used to control multiplexers. The parent
-device tree node must be a device node to provide register r/w access.
-
-Required properties:
-- compatible : should be one of
- "reg-mux" : if parent device of mux controller is not syscon device
- "mmio-mux" : if parent device of mux controller is syscon device
-- #mux-control-cells : <1>
-- mux-reg-masks : an array of register offset and pre-shifted bitfield mask
- pairs, each describing a single mux control.
-* Standard mux-controller bindings as decribed in mux-controller.txt
-
-Optional properties:
-- idle-states : if present, the state the muxes will have when idle. The
- special state MUX_IDLE_AS_IS is the default.
-
-The multiplexer state of each multiplexer is defined as the value of the
-bitfield described by the corresponding register offset and bitfield mask
-pair in the mux-reg-masks array.
-
-Example 1:
-The parent device of mux controller is not a syscon device.
-
-&i2c0 {
- fpga@66 { // fpga connected to i2c
- compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
- "simple-mfd";
- reg = <0x66>;
-
- mux: mux-controller {
- compatible = "reg-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
- <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
- };
- };
-};
-
-mdio-mux-1 {
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 0>;
- mdio-parent-bus = <&emdio1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@8 {
- reg = <0x8>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-mdio-mux-2 {
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 1>;
- mdio-parent-bus = <&emdio2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-Example 2:
-The parent device of mux controller is syscon device.
-
-syscon {
- compatible = "syscon";
-
- mux: mux-controller {
- compatible = "mmio-mux";
- #mux-control-cells = <1>;
-
- mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
- <0x3 0x40>, /* 1: reg 0x3, bit 6 */
- idle-states = <MUX_IDLE_AS_IS>, <0>;
- };
-};
-
-video-mux {
- compatible = "video-mux";
- mux-controls = <&mux 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- ports {
- /* inputs 0..3 */
- port@0 {
- reg = <0>;
- };
- port@1 {
- reg = <1>;
- };
- port@2 {
- reg = <2>;
- };
- port@3 {
- reg = <3>;
- };
-
- /* output */
- port@4 {
- reg = <4>;
- };
- };
-};
diff --git a/Documentation/devicetree/bindings/mux/reg-mux.yaml b/Documentation/devicetree/bindings/mux/reg-mux.yaml
new file mode 100644
index 000000000000..60d5746eb39d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mux/reg-mux.yaml
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mux/reg-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Generic register bitfield-based multiplexer controller bindings
+
+maintainers:
+ - Peter Rosin <peda@axentia.se>
+
+description: |+
+ Define register bitfields to be used to control multiplexers. The parent
+ device tree node must be a device node to provide register r/w access.
+
+properties:
+ compatible:
+ enum:
+ - reg-mux # parent device of mux controller is not syscon device
+ - mmio-mux # parent device of mux controller is syscon device
+
+ reg: true
+
+ '#mux-control-cells':
+ const: 1
+
+ mux-reg-masks:
+ description: an array of register offset and pre-shifted bitfield mask
+ pairs, each describing a single mux control.
+
+ idle-states: true
+
+required:
+ - compatible
+ - mux-reg-masks
+ - '#mux-control-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ /* The parent device of mux controller is not a syscon device. */
+
+ #include <dt-bindings/mux/mux.h>
+
+ mux-controller {
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks =
+ <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
+ };
+
+ mdio-mux-1 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux1 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 {
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux1 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ - |
+ /* The parent device of mux controller is syscon device. */
+
+ #include <dt-bindings/mux/mux.h>
+ syscon@1000 {
+ compatible = "fsl,imx7d-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon", "simple-mfd";
+ reg = <0x1000 0x100>;
+
+ mux2: mux-controller {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+
+ mux-reg-masks =
+ <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
+ <0x3 0x40>; /* 1: reg 0x3, bit 6 */
+ idle-states = <MUX_IDLE_AS_IS>, <0>;
+ };
+ };
+
+ video-mux {
+ compatible = "video-mux";
+ mux-controls = <&mux2 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* inputs 0..3 */
+ port@0 {
+ reg = <0>;
+ };
+ port@1 {
+ reg = <1>;
+ };
+ port@2 {
+ reg = <2>;
+ };
+ port@3 {
+ reg = <3>;
+ };
+
+ /* output */
+ port@4 {
+ reg = <4>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
index 0467441d7037..608e1d62bed5 100644
--- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml
@@ -43,7 +43,6 @@ allOf:
properties:
clocks:
minItems: 3
- maxItems: 4
items:
- description: GMAC main clock
- description: First parent clock of the internal mux
@@ -52,7 +51,6 @@ allOf:
clock-names:
minItems: 3
- maxItems: 4
items:
- const: stmmaceth
- const: clkin0
diff --git a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
index 2f46e45dcd60..a93d2f165899 100644
--- a/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
+++ b/Documentation/devicetree/bindings/net/brcm,bcm4908-enet.yaml
@@ -23,14 +23,12 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RX interrupt
- description: TX interrupt
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: rx
- const: tx
diff --git a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt b/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt
index b58843f29591..deb9e852ea27 100644
--- a/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt
+++ b/Documentation/devicetree/bindings/net/brcm,mdio-mux-iproc.txt
@@ -17,7 +17,7 @@ Optional properties:
- clocks: phandle of the core clock which drives the mdio block.
Additional information regarding generic multiplexer properties can be found
-at- Documentation/devicetree/bindings/net/mdio-mux.txt
+at- Documentation/devicetree/bindings/net/mdio-mux.yaml
for example:
diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
index 798fa5fb7bb2..f84e31348d80 100644
--- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
+++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml
@@ -30,14 +30,12 @@ properties:
- description: interrupt line0
- description: interrupt line1
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: int0
- const: int1
minItems: 1
- maxItems: 2
clocks:
items:
diff --git a/Documentation/devicetree/bindings/net/can/c_can.txt b/Documentation/devicetree/bindings/net/can/c_can.txt
index 2d504256b0d8..366479806acb 100644
--- a/Documentation/devicetree/bindings/net/can/c_can.txt
+++ b/Documentation/devicetree/bindings/net/can/c_can.txt
@@ -19,10 +19,10 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only:
- power-domains : Should contain a phandle to a PM domain provider node
and an args specifier containing the DCAN device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
- clocks : CAN functional clock phandle. This property is as per the
binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
Optional properties:
- syscon-raminit : Handle to system control region that contains the
diff --git a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml
index d730fe5a4355..d159ac78cec1 100644
--- a/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml
+++ b/Documentation/devicetree/bindings/net/dsa/brcm,sf2.yaml
@@ -48,14 +48,12 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: switch's main clock
- description: dividing of the switch core clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_switch
- const: sw_switch_mdiv
diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.txt b/Documentation/devicetree/bindings/net/mdio-gpio.txt
deleted file mode 100644
index 4d91a36c5cf5..000000000000
--- a/Documentation/devicetree/bindings/net/mdio-gpio.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-MDIO on GPIOs
-
-Currently defined compatibles:
-- virtual,gpio-mdio
-- microchip,mdio-smi0
-
-MDC and MDIO lines connected to GPIO controllers are listed in the
-gpios property as described in section VIII.1 in the following order:
-
-MDC, MDIO.
-
-Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
-node.
-
-Example:
-
-aliases {
- mdio-gpio0 = &mdio0;
-};
-
-mdio0: mdio {
- compatible = "virtual,mdio-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- gpios = <&qe_pio_a 11
- &qe_pio_c 6>;
-};
diff --git a/Documentation/devicetree/bindings/net/mdio-gpio.yaml b/Documentation/devicetree/bindings/net/mdio-gpio.yaml
new file mode 100644
index 000000000000..1d83b8dcce2c
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio-gpio.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MDIO on GPIOs
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+ - Heiner Kallweit <hkallweit1@gmail.com>
+ - Russell King <linux@armlinux.org.uk>
+
+allOf:
+ - $ref: "mdio.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - virtual,mdio-gpio
+ - microchip,mdio-smi0
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ gpios:
+ minItems: 2
+ items:
+ - description: MDC
+ - description: MDIO
+ - description: MDO
+
+#Note: Each gpio-mdio bus should have an alias correctly numbered in "aliases"
+#node.
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ aliases {
+ mdio-gpio0 = &mdio0;
+ };
+
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ gpios = <&qe_pio_a 11>,
+ <&qe_pio_c 6>;
+ ethphy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt b/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt
deleted file mode 100644
index 694987d3c17a..000000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux-gpio.txt
+++ /dev/null
@@ -1,119 +0,0 @@
-Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
-
-This is a special case of a MDIO bus multiplexer. One or more GPIO
-lines are used to control which child bus is connected.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : mdio-mux-gpio.
-- gpios : GPIO specifiers for each GPIO line. One or more must be specified.
-
-
-Example :
-
- /* The parent MDIO bus. */
- smi1: mdio@1180000001900 {
- compatible = "cavium,octeon-3860-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x11800 0x00001900 0x0 0x40>;
- };
-
- /*
- An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
- pair of GPIO lines. Child busses 2 and 3 populated with 4
- PHYs each.
- */
- mdio-mux {
- compatible = "mdio-mux-gpio";
- gpios = <&gpio1 3 0>, <&gpio1 4 0>;
- mdio-parent-bus = <&smi1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy11: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy12: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy13: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy14: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- };
-
- mdio@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy21: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy22: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy23: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy24: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml b/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml
new file mode 100644
index 000000000000..71c25c4580ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio-mux-gpio.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description:
+ This is a special case of a MDIO bus multiplexer. One or more GPIO
+ lines are used to control which child bus is connected.
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ const: mdio-mux-gpio
+
+ gpios:
+ description:
+ List of GPIOs used to control the multiplexer, least significant bit first.
+ minItems: 1
+ maxItems: 32
+
+required:
+ - compatible
+ - gpios
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ /*
+ An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
+ pair of GPIO lines. Child busses 2 and 3 populated with 4
+ PHYs each.
+ */
+ mdio-mux {
+ compatible = "mdio-mux-gpio";
+ gpios = <&gpio1 3 0>, <&gpio1 4 0>;
+ mdio-parent-bus = <&smi1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <1>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@2 {
+ reg = <2>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@3 {
+ reg = <3>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ ethernet-phy@4 {
+ reg = <4>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <10 8>; /* Pin 10, active low */
+ };
+ };
+
+ mdio@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ reg = <1>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@2 {
+ reg = <2>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@3 {
+ reg = <3>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ ethernet-phy@4 {
+ reg = <4>;
+ marvell,reg-init = <3 0x10 0 0x5777>,
+ <3 0x11 0 0x00aa>,
+ <3 0x12 0 0x4105>,
+ <3 0x13 0 0x0a60>;
+ interrupt-parent = <&gpio>;
+ interrupts = <12 8>; /* Pin 12, active low */
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
deleted file mode 100644
index 065e8bdb957d..000000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-Properties for an MDIO bus multiplexer controlled by a memory-mapped device
-
-This is a special case of a MDIO bus multiplexer. A memory-mapped device,
-like an FPGA, is used to control which child bus is connected. The mdio-mux
-node must be a child of the memory-mapped device. The driver currently only
-supports devices with 8, 16 or 32-bit registers.
-
-Required properties in addition to the generic multiplexer properties:
-
-- compatible : string, must contain "mdio-mux-mmioreg"
-
-- reg : integer, contains the offset of the register that controls the bus
- multiplexer. The size field in the 'reg' property is the size of
- register, and must therefore be 1, 2, or 4.
-
-- mux-mask : integer, contains an eight-bit mask that specifies which
- bits in the register control the actual bus multiplexer. The
- 'reg' property of each child mdio-mux node must be constrained by
- this mask.
-
-Example:
-
-The FPGA node defines a memory-mapped FPGA with a register space of 0x30 bytes.
-For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
-A bitmask of 0x6 means that bits 1 and 2 (bit 0 is lsb) are the bits on
-BRDCFG1 that control the actual mux.
-
- /* The FPGA node */
- fpga: board-control@3,0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "fsl,p5020ds-fpga", "fsl,fpga-ngpixis";
- reg = <3 0 0x30>;
- ranges = <0 3 0 0x30>;
-
- mdio-mux-emi2 {
- compatible = "mdio-mux-mmioreg", "mdio-mux";
- mdio-parent-bus = <&xmdio0>;
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <9 1>; // BRDCFG1
- mux-mask = <0x6>; // EMI2
-
- emi2_slot1: mdio@0 { // Slot 1 XAUI (FM2)
- reg = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_xgmii_slot1: ethernet-phy@0 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <4>;
- };
- };
-
- emi2_slot2: mdio@2 { // Slot 2 XAUI (FM1)
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy_xgmii_slot2: ethernet-phy@4 {
- compatible = "ethernet-phy-ieee802.3-c45";
- reg = <0>;
- };
- };
- };
- };
-
- /* The parent MDIO bus. */
- xmdio0: mdio@f1000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,fman-xmdio";
- reg = <0xf1000 0x1000>;
- interrupts = <100 1 0 0>;
- };
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml
new file mode 100644
index 000000000000..cf86bb0b0b62
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio-mux-mmioreg.yaml
@@ -0,0 +1,78 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ This is a special case of a MDIO bus multiplexer. A memory-mapped device,
+ like an FPGA, is used to control which child bus is connected. The mdio-mux
+ node must be a child of the memory-mapped device. The driver currently only
+ supports devices with 8, 16 or 32-bit registers.
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: mdio-mux-mmioreg
+ - const: mdio-mux
+
+ reg:
+ description: Contains the offset of the register that controls the bus
+ multiplexer. The size field in the 'reg' property is the size of register,
+ and must therefore be 1, 2, or 4.
+ maxItems: 1
+
+ mux-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Contains an eight-bit mask that specifies which bits in the
+ register control the actual bus multiplexer. The 'reg' property of each
+ child mdio-mux node must be constrained by this mask.
+
+required:
+ - compatible
+ - reg
+ - mux-mask
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio-mux@9 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&xmdio0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <9 1>; // BRDCFG1
+ mux-mask = <0x6>; // EMI2
+
+ mdio@0 { // Slot 1 XAUI (FM2)
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ phy_xgmii_slot1: ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
+
+ mdio@2 { // Slot 2 XAUI (FM1)
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@4 {
+ compatible = "ethernet-phy-ieee802.3-c45";
+ reg = <4>;
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt
deleted file mode 100644
index 534e38058fe0..000000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.txt
+++ /dev/null
@@ -1,82 +0,0 @@
-Properties for an MDIO bus multiplexer consumer device
-
-This is a special case of MDIO mux when MDIO mux is defined as a consumer
-of a mux producer device. The mux producer can be of any type like mmio mux
-producer, gpio mux producer or generic register based mux producer.
-
-Required properties in addition to the MDIO Bus multiplexer properties:
-
-- compatible : should be "mmio-mux-multiplexer"
-- mux-controls : mux controller node to use for operating the mux
-- mdio-parent-bus : phandle to the parent MDIO bus.
-
-each child node of mdio bus multiplexer consumer device represent a mdio
-bus.
-
-for more information please refer
-Documentation/devicetree/bindings/mux/mux-controller.txt
-and Documentation/devicetree/bindings/net/mdio-mux.txt
-
-Example:
-In below example the Mux producer and consumer are separate nodes.
-
-&i2c0 {
- fpga@66 { // fpga connected to i2c
- compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
- "simple-mfd";
- reg = <0x66>;
-
- mux: mux-controller { // Mux Producer
- compatible = "reg-mux";
- #mux-control-cells = <1>;
- mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
- <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
- };
- };
-};
-
-mdio-mux-1 { // Mux consumer
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 0>;
- mdio-parent-bus = <&emdio1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@8 {
- reg = <0x8>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
-
-mdio-mux-2 { // Mux consumer
- compatible = "mdio-mux-multiplexer";
- mux-controls = <&mux 1>;
- mdio-parent-bus = <&emdio2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@0 {
- reg = <0x0>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- mdio@1 {
- reg = <0x1>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- ..
- ..
-};
diff --git a/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml
new file mode 100644
index 000000000000..282987074ee4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio-mux-multiplexer.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Properties for an MDIO bus multiplexer consumer device
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ This is a special case of MDIO mux when MDIO mux is defined as a consumer
+ of a mux producer device. The mux producer can be of any type like mmio mux
+ producer, gpio mux producer or generic register based mux producer.
+
+
+allOf:
+ - $ref: /schemas/net/mdio-mux.yaml#
+
+properties:
+ compatible:
+ const: mdio-mux-multiplexer
+
+ mux-controls:
+ maxItems: 1
+
+required:
+ - compatible
+ - mux-controls
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mux: mux-controller { // Mux Producer
+ compatible = "reg-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
+ <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
+ };
+
+ mdio-mux-1 { // Mux consumer
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 0>;
+ mdio-parent-bus = <&emdio1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@8 {
+ reg = <0x8>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ mdio-mux-2 { // Mux consumer
+ compatible = "mdio-mux-multiplexer";
+ mux-controls = <&mux 1>;
+ mdio-parent-bus = <&emdio2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mdio@1 {
+ reg = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/net/mdio-mux.txt b/Documentation/devicetree/bindings/net/mdio-mux.txt
deleted file mode 100644
index f58571f36570..000000000000
--- a/Documentation/devicetree/bindings/net/mdio-mux.txt
+++ /dev/null
@@ -1,129 +0,0 @@
-Common MDIO bus multiplexer/switch properties.
-
-An MDIO bus multiplexer/switch will have several child busses that are
-numbered uniquely in a device dependent manner. The nodes for an MDIO
-bus multiplexer/switch will have one child node for each child bus.
-
-Required properties:
-- #address-cells = <1>;
-- #size-cells = <0>;
-
-Optional properties:
-- mdio-parent-bus : phandle to the parent MDIO bus.
-
-- Other properties specific to the multiplexer/switch hardware.
-
-Required properties for child nodes:
-- #address-cells = <1>;
-- #size-cells = <0>;
-- reg : The sub-bus number.
-
-
-Example :
-
- /* The parent MDIO bus. */
- smi1: mdio@1180000001900 {
- compatible = "cavium,octeon-3860-mdio";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x11800 0x00001900 0x0 0x40>;
- };
-
- /*
- An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
- pair of GPIO lines. Child busses 2 and 3 populated with 4
- PHYs each.
- */
- mdio-mux {
- compatible = "mdio-mux-gpio";
- gpios = <&gpio1 3 0>, <&gpio1 4 0>;
- mdio-parent-bus = <&smi1>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- mdio@2 {
- reg = <2>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy11: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy12: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy13: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- phy14: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <10 8>; /* Pin 10, active low */
- };
- };
-
- mdio@3 {
- reg = <3>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- phy21: ethernet-phy@1 {
- reg = <1>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy22: ethernet-phy@2 {
- reg = <2>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy23: ethernet-phy@3 {
- reg = <3>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- phy24: ethernet-phy@4 {
- reg = <4>;
- marvell,reg-init = <3 0x10 0 0x5777>,
- <3 0x11 0 0x00aa>,
- <3 0x12 0 0x4105>,
- <3 0x13 0 0x0a60>;
- interrupt-parent = <&gpio>;
- interrupts = <12 8>; /* Pin 12, active low */
- };
- };
- };
diff --git a/Documentation/devicetree/bindings/net/mdio-mux.yaml b/Documentation/devicetree/bindings/net/mdio-mux.yaml
new file mode 100644
index 000000000000..d169adf5d9f4
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/mdio-mux.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/mdio-mux.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common MDIO bus multiplexer/switch properties.
+
+maintainers:
+ - Andrew Lunn <andrew@lunn.ch>
+
+description: |+
+ An MDIO bus multiplexer/switch will have several child busses that are
+ numbered uniquely in a device dependent manner. The nodes for an MDIO
+ bus multiplexer/switch will have one child node for each child bus.
+
+properties:
+ $nodename:
+ pattern: '^mdio-mux[\-@]?'
+
+ mdio-parent-bus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ The phandle of the MDIO bus that this multiplexer's master-side port is
+ connected to.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+patternProperties:
+ '^mdio@[0-9a-f]+$':
+ type: object
+
+ properties:
+ reg:
+ maxItems: 1
+ description: The sub-bus number.
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
index 56f2235f5fb5..d7652596a09b 100644
--- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml
@@ -91,7 +91,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 3
items:
- description: Combined signal for various interrupt events
- description: The interrupt to manage the remote wake-up packet detection
@@ -99,7 +98,6 @@ properties:
interrupt-names:
minItems: 1
- maxItems: 3
items:
- const: macirq
- const: eth_wake_irq
diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
index 27eb6066793f..19c7bd482a51 100644
--- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
+++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml
@@ -46,7 +46,6 @@ properties:
clocks:
minItems: 3
- maxItems: 5
items:
- description: GMAC main clock
- description: MAC TX clock
diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
index f90557f6deb8..b9589a0daa5c 100644
--- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml
@@ -25,14 +25,12 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml
index 81bae060cbde..82bc6c486ca3 100644
--- a/Documentation/devicetree/bindings/pci/loongson.yaml
+++ b/Documentation/devicetree/bindings/pci/loongson.yaml
@@ -24,7 +24,6 @@ properties:
reg:
minItems: 1
- maxItems: 2
items:
- description: CFG0 standard config space register
- description: CFG1 extended config space register
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
index e7b1f9892da4..742206dbd965 100644
--- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
+++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml
@@ -70,7 +70,6 @@ properties:
reset-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: mac
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
index 04251d71f56b..fb95c276a986 100644
--- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
+++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml
@@ -26,14 +26,12 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: PCIe host controller
- description: builtin MSI controller
interrupt-names:
minItems: 1
- maxItems: 2
items:
- const: pcie
- const: msi
diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
deleted file mode 100644
index 47202a2938f2..000000000000
--- a/Documentation/devicetree/bindings/pci/pci-keystone.txt
+++ /dev/null
@@ -1,115 +0,0 @@
-TI Keystone PCIe interface
-
-Keystone PCI host Controller is based on the Synopsys DesignWare PCI
-hardware version 3.65. It shares common functions with the PCIe DesignWare
-core driver and inherits common properties defined in
-Documentation/devicetree/bindings/pci/designware-pcie.txt
-
-Please refer to Documentation/devicetree/bindings/pci/designware-pcie.txt
-for the details of DesignWare DT bindings. Additional properties are
-described here as well as properties that are not applicable.
-
-Required Properties:-
-
-compatibility: Should be "ti,keystone-pcie" for RC on Keystone2 SoC
- Should be "ti,am654-pcie-rc" for RC on AM654x SoC
-reg: Three register ranges as listed in the reg-names property
-reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
- TI specific application registers, "config" for the
- configuration space address
-
-pcie_msi_intc : Interrupt controller device node for MSI IRQ chip
- interrupt-cells: should be set to 1
- interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
- (required if the compatible is "ti,keystone-pcie")
-msi-map: As specified in Documentation/devicetree/bindings/pci/pci-msi.txt
- (required if the compatible is "ti,am654-pcie-rc".
-
-ti,syscon-pcie-id : phandle to the device control module required to set device
- id and vendor id.
-ti,syscon-pcie-mode : phandle to the device control module required to configure
- PCI in either RC mode or EP mode.
-
- Example:
- pcie_msi_intc: msi-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
- };
-
-pcie_intc: Interrupt controller device node for Legacy IRQ chip
- interrupt-cells: should be set to 1
-
- Example:
- pcie_intc: legacy-interrupt-controller {
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
- };
-
-Optional properties:-
- phys: phandle to generic Keystone SerDes PHY for PCI
- phy-names: name of the generic Keystone SerDes PHY for PCI
- - If boot loader already does PCI link establishment, then phys and
- phy-names shouldn't be present.
- interrupts: platform interrupt for error interrupts.
-
-DesignWare DT Properties not applicable for Keystone PCI
-
-1. pcie_bus clock-names not used. Instead, a phandle to phys is used.
-
-AM654 PCIe Endpoint
-===================
-
-Required Properties:-
-
-compatibility: Should be "ti,am654-pcie-ep" for EP on AM654x SoC
-reg: Four register ranges as listed in the reg-names property
-reg-names: "dbics" for the DesignWare PCIe registers, "app" for the
- TI specific application registers, "atu" for the
- Address Translation Unit configuration registers and
- "addr_space" used to map remote RC address space
-num-ib-windows: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-num-ob-windows: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-num-lanes: As specified in
- Documentation/devicetree/bindings/pci/designware-pcie.txt
-power-domains: As documented by the generic PM domain bindings in
- Documentation/devicetree/bindings/power/power_domain.txt.
-ti,syscon-pcie-mode: phandle to the device control module required to configure
- PCI in either RC mode or EP mode.
-
-Optional properties:-
-
-phys: list of PHY specifiers (used by generic PHY framework)
-phy-names: must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
- number of lanes as specified in *num-lanes* property.
-("phys" and "phy-names" DT bindings are specified in
-Documentation/devicetree/bindings/phy/phy-bindings.txt)
-interrupts: platform interrupt for error interrupts.
-
-pcie-ep {
- compatible = "ti,am654-pcie-ep";
- reg = <0x5500000 0x1000>, <0x5501000 0x1000>,
- <0x10000000 0x8000000>, <0x5506000 0x1000>;
- reg-names = "app", "dbics", "addr_space", "atu";
- power-domains = <&k3_pds 120>;
- ti,syscon-pcie-mode = <&pcie0_mode>;
- num-lanes = <1>;
- num-ib-windows = <16>;
- num-ob-windows = <16>;
- interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
-};
diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
new file mode 100644
index 000000000000..78c217d362a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-ep.yaml
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ti,am65-pci-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI AM65 PCI Endpoint
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+allOf:
+ - $ref: pci-ep.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-ep
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: app
+ - const: dbics
+ - const: addr_space
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ interrupts:
+ minItems: 1
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - max-link-speed
+ - power-domains
+ - ti,syscon-pcie-mode
+ - dma-coherent
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ pcie0_ep: pcie-ep@5500000 {
+ compatible = "ti,am654-pcie-ep";
+ reg = <0x5500000 0x1000>,
+ <0x5501000 0x1000>,
+ <0x10000000 0x8000000>,
+ <0x5506000 0x1000>;
+ reg-names = "app", "dbics", "addr_space", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ num-ib-windows = <16>;
+ num-ob-windows = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ };
diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
new file mode 100644
index 000000000000..834dc1c1743c
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI AM65 PCI Host
+
+maintainers:
+ - Kishon Vijay Abraham I <kishon@ti.com>
+
+allOf:
+ - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-rc
+ - ti,keystone-pcie
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: app
+ - const: dbics
+ - const: config
+ - const: atu
+
+ power-domains:
+ maxItems: 1
+
+ ti,syscon-pcie-id:
+ description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ ti,syscon-pcie-mode:
+ description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ msi-map: true
+
+ dma-coherent: true
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - max-link-speed
+ - ti,syscon-pcie-id
+ - ti,syscon-pcie-mode
+ - ranges
+
+if:
+ properties:
+ compatible:
+ enum:
+ - ti,am654-pcie-rc
+then:
+ required:
+ - dma-coherent
+ - power-domains
+ - msi-map
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/soc/ti,sci_pm_domain.h>
+
+ pcie0_rc: pcie@5500000 {
+ compatible = "ti,am654-pcie-rc";
+ reg = <0x5500000 0x1000>,
+ <0x5501000 0x1000>,
+ <0x10000000 0x2000>,
+ <0x5506000 0x1000>;
+ reg-names = "app", "dbics", "config", "atu";
+ power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x81000000 0 0 0x10020000 0 0x00010000>,
+ <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
+ ti,syscon-pcie-id = <&pcie_devid>;
+ ti,syscon-pcie-mode = <&pcie0_mode>;
+ bus-range = <0x0 0xff>;
+ num-viewport = <16>;
+ max-link-speed = <2>;
+ dma-coherent;
+ interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
+ msi-map = <0x0 &gic_its 0x0 0x10000>;
+ device_type = "pci";
+ };
diff --git a/Documentation/devicetree/bindings/perf/arm,cmn.yaml b/Documentation/devicetree/bindings/perf/arm,cmn.yaml
index e4fcc0de25e2..42424ccbdd0c 100644
--- a/Documentation/devicetree/bindings/perf/arm,cmn.yaml
+++ b/Documentation/devicetree/bindings/perf/arm,cmn.yaml
@@ -21,7 +21,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 4
items:
- description: Overflow interrupt for DTC0
- description: Overflow interrupt for DTC1
diff --git a/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
index 9a2e779e6d38..0f0bcde9eb88 100644
--- a/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/brcm,bcm63xx-usbh-phy.yaml
@@ -28,7 +28,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: usbh
- const: usb_ref
diff --git a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
index 5f9e91bfb5ff..43a4b880534c 100644
--- a/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.yaml
@@ -22,7 +22,6 @@ properties:
reg:
minItems: 1
- maxItems: 6
items:
- description: the base CTRL register
- description: XHCI EC register
@@ -33,7 +32,6 @@ properties:
reg-names:
minItems: 1
- maxItems: 6
items:
- const: ctrl
- const: xhci_ec
@@ -51,7 +49,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: sw_usb
- const: sw_usb3
diff --git a/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
index 04edda504ab6..cb1aa325336f 100644
--- a/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/brcm,sata-phy.yaml
@@ -35,7 +35,6 @@ properties:
reg-names:
minItems: 1
- maxItems: 2
items:
- const: phy
- const: phy-ctrl
diff --git a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
index b8a7651a3d9a..ef9d9d4e6875 100644
--- a/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
+++ b/Documentation/devicetree/bindings/phy/mediatek,tphy.yaml
@@ -131,7 +131,6 @@ patternProperties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz)
- description: Reference clock of analog phy
@@ -141,7 +140,6 @@ patternProperties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: da_ref
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
index 84383e2e0b34..e71b32c9c0d1 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
@@ -31,14 +31,12 @@ properties:
resets:
minItems: 1
- maxItems: 2
items:
- description: Sierra PHY reset.
- description: Sierra APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: sierra_reset
- const: sierra_apb
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
index 320a232c7208..bd9ae11c9994 100644
--- a/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
+++ b/Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
@@ -52,28 +52,24 @@ properties:
reg:
minItems: 1
- maxItems: 2
items:
- description: Offset of the Torrent PHY configuration registers.
- description: Offset of the DPTX PHY configuration registers.
reg-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_phy
- const: dptx_phy
resets:
minItems: 1
- maxItems: 2
items:
- description: Torrent PHY reset.
- description: Torrent APB reset. This is optional.
reset-names:
minItems: 1
- maxItems: 2
items:
- const: torrent_reset
- const: torrent_apb
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
index 17f132ce5516..35296c588e78 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-hs.yaml
@@ -30,7 +30,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
diff --git a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
index 17fd7f6b83bb..6cf5c6c06072 100644
--- a/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,ipq806x-usb-phy-ss.yaml
@@ -30,7 +30,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: ref
- const: xo
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 7808ec8bc712..a2de5202eb5e 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -49,7 +49,6 @@ properties:
reg:
minItems: 1
- maxItems: 2
items:
- description: Address and length of PHY's common serdes block.
- description: Address and length of PHY's DP_COM control block.
diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
index 9f9cf07b7d45..930da598c969 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
@@ -36,7 +36,6 @@ properties:
clocks:
minItems: 2
- maxItems: 3
items:
- description: phy config clock
- description: 19.2 MHz ref clk
@@ -44,7 +43,6 @@ properties:
clock-names:
minItems: 2
- maxItems: 3
items:
- const: cfg_ahb
- const: ref
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
index 0f358d5b84ef..d5dc5a3cdceb 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml
@@ -39,7 +39,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: fck
- const: usb_x1
@@ -61,7 +60,6 @@ properties:
resets:
minItems: 1
- maxItems: 2
items:
- description: reset of USB 2.0 host side
- description: reset of USB 2.0 peripheral side
diff --git a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
index f3ef738a3ff6..b8483f9edbfc 100644
--- a/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/renesas,usb3-phy.yaml
@@ -33,7 +33,6 @@ properties:
# If you want to use the ssc, the clock-frequency of usb_extal
# must not be 0.
minItems: 2
- maxItems: 3
items:
- const: usb3-if # The funcional clock
- const: usb3s_clk # The usb3's external clock
diff --git a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
index ccdd9e3820d7..3f94f6944740 100644
--- a/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
+++ b/Documentation/devicetree/bindings/pinctrl/actions,s500-pinctrl.yaml
@@ -26,7 +26,6 @@ properties:
- description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
- description: PAD Drive Capacity Select
minItems: 1
- maxItems: 4
clocks:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
index d30f85cc395e..f005abac7079 100644
--- a/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
+++ b/Documentation/devicetree/bindings/power/amlogic,meson-ee-pwrc.yaml
@@ -37,7 +37,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: vpu
- const: vapb
diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
deleted file mode 100644
index 49aba15dff8b..000000000000
--- a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.txt
+++ /dev/null
@@ -1,100 +0,0 @@
-DT bindings for the Renesas R-Mobile System Controller
-
-== System Controller Node ==
-
-The R-Mobile System Controller provides the following functions:
- - Boot mode management,
- - Reset generation,
- - Power management.
-
-Required properties:
-- compatible: Should be "renesas,sysc-<soctype>", "renesas,sysc-rmobile" as
- fallback.
- Examples with soctypes are:
- - "renesas,sysc-r8a73a4" (R-Mobile APE6)
- - "renesas,sysc-r8a7740" (R-Mobile A1)
- - "renesas,sysc-sh73a0" (SH-Mobile AG5)
-- reg: Two address start and address range blocks for the device:
- - The first block refers to the normally accessible registers,
- - the second block refers to the registers protected by the HPB
- semaphore.
-
-Optional nodes:
-- pm-domains: This node contains a hierarchy of PM domain nodes, which should
- match the Power Area Hierarchy in the Power Domain Specifications section of
- the device's datasheet.
-
-
-== PM Domain Nodes ==
-
-Each of the PM domain nodes represents a PM domain, as documented by the
-generic PM domain bindings in
-Documentation/devicetree/bindings/power/power-domain.yaml.
-
-The nodes should be named by the real power area names, and thus their names
-should be unique.
-
-Required properties:
- - #power-domain-cells: Must be 0.
-
-Optional properties:
-- reg: If the PM domain is not always-on, this property must contain the bit
- index number for the corresponding power area in the various Power
- Control and Status Registers. The parent's node must contain the
- following two properties:
- - #address-cells: Must be 1,
- - #size-cells: Must be 0.
- If the PM domain is always-on, this property must be omitted.
-
-
-Example:
-
-This shows a subset of the r8a7740 PM domain hierarchy, containing the
-C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP domain,
-which is a subdomain of A4S.
-
- sysc: system-controller@e6180000 {
- compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
- reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
-
- pm-domains {
- pd_c5: c5 {
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- pd_a4s: a4s@10 {
- reg = <10>;
- #address-cells = <1>;
- #size-cells = <0>;
- #power-domain-cells = <0>;
-
- pd_a3sp: a3sp@11 {
- reg = <11>;
- #power-domain-cells = <0>;
- };
- };
-
- pd_a4su: a4su@20 {
- reg = <20>;
- #power-domain-cells = <0>;
- };
- };
- };
- };
-
-
-== PM Domain Consumers ==
-
-Hardware blocks belonging to a PM domain should contain a "power-domains"
-property that is a phandle pointing to the corresponding PM domain node.
-
-Example:
-
- tpu: pwm@e6600000 {
- compatible = "renesas,tpu-r8a7740", "renesas,tpu";
- reg = <0xe6600000 0x100>;
- clocks = <&mstp3_clks R8A7740_CLK_TPU0>;
- power-domains = <&pd_a3sp>;
- #pwm-cells = <3>;
- };
diff --git a/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml
new file mode 100644
index 000000000000..559718997de7
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/renesas,sysc-rmobile.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/renesas,sysc-rmobile.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas R-Mobile System Controller
+
+maintainers:
+ - Geert Uytterhoeven <geert+renesas@glider.be>
+ - Magnus Damm <magnus.damm@gmail.com>
+
+description: |
+ The R-Mobile System Controller provides the following functions:
+ - Boot mode management,
+ - Reset generation,
+ - Power management.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - renesas,sysc-r8a73a4 # R-Mobile APE6
+ - renesas,sysc-r8a7740 # R-Mobile A1
+ - renesas,sysc-sh73a0 # SH-Mobile AG5
+ - const: renesas,sysc-rmobile # Generic SH/R-Mobile
+
+ reg:
+ items:
+ - description: Normally accessible register block
+ - description: Register block protected by the HPB semaphore
+
+ pm-domains:
+ type: object
+ description: |
+ This node contains a hierarchy of PM domain nodes, which should match the
+ Power Area Hierarchy in the Power Domain Specifications section of the
+ device's datasheet.
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ additionalProperties:
+ $ref: "#/$defs/pd-node"
+
+required:
+ - compatible
+ - reg
+ - pm-domains
+
+additionalProperties: false
+
+$defs:
+ pd-node:
+ type: object
+ description:
+ PM domain node representing a PM domain. This node hould be named by
+ the real power area name, and thus its name should be unique.
+
+ properties:
+ reg:
+ maxItems: 1
+ description:
+ If the PM domain is not always-on, this property must contain the
+ bit index number for the corresponding power area in the various
+ Power Control and Status Registers.
+ If the PM domain is always-on, this property must be omitted.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ '#power-domain-cells':
+ const: 0
+
+ required:
+ - '#power-domain-cells'
+
+ additionalProperties:
+ $ref: "#/$defs/pd-node"
+
+examples:
+ - |
+ // This shows a subset of the r8a7740 PM domain hierarchy, containing the
+ // C5 "always-on" domain, 2 of its subdomains (A4S and A4SU), and the A3SP
+ // domain, which is a subdomain of A4S.
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,sysc-r8a7740", "renesas,sysc-rmobile";
+ reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
+
+ pm-domains {
+ pd_c5: c5 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_a4s: a4s@10 {
+ reg = <10>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <0>;
+
+ pd_a3sp: a3sp@11 {
+ reg = <11>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ pd_a4su: a4su@20 {
+ reg = <20>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/property-units.txt b/Documentation/devicetree/bindings/property-units.txt
deleted file mode 100644
index 218f99fa311f..000000000000
--- a/Documentation/devicetree/bindings/property-units.txt
+++ /dev/null
@@ -1,48 +0,0 @@
-Standard Unit Suffixes for Property names
-
-Properties which have a unit of measure are recommended to have a unit
-suffix appended to the property name. The list below contains the
-recommended suffixes. Other variations exist in bindings, but should not
-be used in new bindings or added here. The inconsistency in the unit
-prefixes is due to selecting the most commonly used variants.
-
-It is also recommended to use the units listed here and not add additional
-unit prefixes.
-
-Time/Frequency
-----------------------------------------
--mhz : megahertz
--hz : hertz (preferred)
--sec : second
--ms : millisecond
--us : microsecond
--ns : nanosecond
--ps : picosecond
-
-Distance
-----------------------------------------
--mm : millimeter
-
-Electricity
-----------------------------------------
--microamp : microampere
--microamp-hours : microampere hour
--ohms : ohm
--micro-ohms : microohm
--microwatt-hours: microwatt hour
--microvolt : microvolt
--picofarads : picofarad
--femtofarads : femtofarad
-
-Temperature
-----------------------------------------
--celsius : degree Celsius
--millicelsius : millidegree Celsius
-
-Pressure
-----------------------------------------
--kpascal : kilopascal
-
-Throughput
-----------------------------------------
--kBps : kilobytes per second
diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
index 7dcab2bf8128..54a7700df08f 100644
--- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml
@@ -37,7 +37,6 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: Module Clock
- description: Bus Clock
diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt
deleted file mode 100644
index 655f6cd4ef46..000000000000
--- a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Broadcom iProc PWM controller device tree bindings
-
-This controller has 4 channels.
-
-Required Properties :
-- compatible: must be "brcm,iproc-pwm"
-- reg: physical base address and length of the controller's registers
-- clocks: phandle + clock specifier pair for the external clock
-- #pwm-cells: Should be 3. See pwm.yaml in this directory for a
- description of the cells format.
-
-Refer to clocks/clock-bindings.txt for generic clock consumer properties.
-
-Example:
-
-pwm: pwm@18031000 {
- compatible = "brcm,iproc-pwm";
- reg = <0x18031000 0x28>;
- clocks = <&osc>;
- #pwm-cells = <3>;
-};
diff --git a/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml
new file mode 100644
index 000000000000..218ab06c34d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/brcm,iproc-pwm.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/brcm,iproc-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom iProc PWM controller
+
+maintainers:
+ - Rafał Miłecki <rafal@milecki.pl>
+
+description:
+ This controller has 4 channels.
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: brcm,iproc-pwm
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ description: external clock
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 3
+
+unevaluatedProperties: false
+
+required:
+ - reg
+ - clocks
+
+examples:
+ - |
+ pwm@18031000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18031000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ };
diff --git a/Documentation/devicetree/bindings/pwm/pwm.yaml b/Documentation/devicetree/bindings/pwm/pwm.yaml
index 7d1f687cee9c..2effe6c0de6b 100644
--- a/Documentation/devicetree/bindings/pwm/pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm.yaml
@@ -24,8 +24,9 @@ additionalProperties: true
examples:
- |
- pwm: pwm@7000a000 {
- compatible = "nvidia,tegra20-pwm";
- reg = <0x7000a000 0x100>;
- #pwm-cells = <2>;
+ pwm: pwm@1c20e00 {
+ compatible = "allwinner,sun7i-a20-pwm";
+ reg = <0x01c20e00 0xc>;
+ clocks = <&osc24M>;
+ #pwm-cells = <3>;
};
diff --git a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
index 3c2fa2e93d1b..7ea1070b4b3a 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,pwm-rcar.yaml
@@ -61,6 +61,19 @@ required:
- reg
- '#pwm-cells'
- clocks
+ - power-domains
+
+if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,pwm-r8a7778
+ - renesas,pwm-r8a7779
+then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
index aa9a4570c906..81ccb2110162 100644
--- a/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/renesas,tpu-pwm.yaml
@@ -9,6 +9,15 @@ title: Renesas R-Car Timer Pulse Unit PWM Controller
maintainers:
- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
+select:
+ properties:
+ compatible:
+ contains:
+ const: renesas,tpu
+ required:
+ - compatible
+ - '#pwm-cells'
+
properties:
compatible:
items:
@@ -58,6 +67,23 @@ required:
- compatible
- reg
- '#pwm-cells'
+ - clocks
+ - power-domains
+
+allOf:
+ - $ref: pwm.yaml#
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - renesas,tpu-r8a73a4
+ - renesas,tpu-r8a7740
+ then:
+ required:
+ - resets
additionalProperties: false
diff --git a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
index 64afdcfb613d..1e6225677e00 100644
--- a/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/st,stm32-rproc.yaml
@@ -72,7 +72,6 @@ properties:
- from local to remote, where ACK from the remote means that communnication
as been stopped on the remote side.
minItems: 1
- maxItems: 4
mbox-names:
items:
@@ -81,7 +80,6 @@ properties:
- const: shutdown
- const: detach
minItems: 1
- maxItems: 4
memory-region:
description:
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
index 461dc1d8d570..463a97c11eff 100644
--- a/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
+++ b/Documentation/devicetree/bindings/remoteproc/ti,keystone-rproc.txt
@@ -48,7 +48,7 @@ The following are the mandatory properties:
bindings for the reset argument specifier as per SoC,
Documentation/devicetree/bindings/reset/ti-syscon-reset.txt
for 66AK2HK/66AK2L/66AK2E SoCs or,
- Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+ Documentation/devicetree/bindings/reset/ti,sci-reset.yaml
for 66AK2G SoCs
- interrupts: Should contain an entry for each value in 'interrupt-names'.
@@ -82,7 +82,7 @@ The following are mandatory properties for Keystone 2 66AK2G SoCs only:
- power-domains: Should contain a phandle to a PM domain provider node
and an args specifier containing the DSP device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
Optional properties:
--------------------
diff --git a/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml
index 73400bc6e91d..c6c12129d6b7 100644
--- a/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml
+++ b/Documentation/devicetree/bindings/remoteproc/ti,omap-remoteproc.yaml
@@ -65,7 +65,7 @@ properties:
OMAP Mailbox specifier denoting the sub-mailbox, to be used for
communication with the remote processor. The specifier format is
as per the bindings,
- Documentation/devicetree/bindings/mailbox/omap-mailbox.txt
+ Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
This property should match with the sub-mailbox node used in
the firmware image.
@@ -116,7 +116,6 @@ properties:
list, in the specified order, each representing the corresponding
internal RAM memory region.
minItems: 1
- maxItems: 3
items:
- const: l2ram
- const: l1pram
diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
index 27c5e34a3ac6..b11ac533f914 100644
--- a/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
+++ b/Documentation/devicetree/bindings/reset/fsl,imx-src.yaml
@@ -59,7 +59,6 @@ properties:
- description: SRC interrupt
- description: CPU WDOG interrupts out of SRC
minItems: 1
- maxItems: 2
'#reset-cells':
const: 1
diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt
deleted file mode 100644
index 8b1cf022f18a..000000000000
--- a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+++ /dev/null
@@ -1,62 +0,0 @@
-Texas Instruments System Control Interface (TI-SCI) Reset Controller
-=====================================================================
-
-Some TI SoCs contain a system controller (like the Power Management Micro
-Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
-the state of the various hardware modules present on the SoC. Communication
-between the host processor running an OS and the system controller happens
-through a protocol called TI System Control Interface (TI-SCI protocol).
-For TI SCI details, please refer to the document,
-Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-TI-SCI Reset Controller Node
-============================
-This reset controller node uses the TI SCI protocol to perform the reset
-management of various hardware modules present on the SoC. Must be a child
-node of the associated TI-SCI system controller node.
-
-Required properties:
---------------------
- - compatible : Should be "ti,sci-reset"
- - #reset-cells : Should be 2. Please see the reset consumer node below for
- usage details.
-
-TI-SCI Reset Consumer Nodes
-===========================
-Each of the reset consumer nodes should have the following properties,
-in addition to their own properties.
-
-Required properties:
---------------------
- - resets : A phandle and reset specifier pair, one pair for each reset
- signal that affects the device, or that the device manages.
- The phandle should point to the TI-SCI reset controller node,
- and the reset specifier should have 2 cell-values. The first
- cell should contain the device ID. The second cell should
- contain the reset mask value used by system controller.
- Please refer to the protocol documentation for these values
- to be used for different devices,
- http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data
-
-Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
-common reset controller usage by consumers.
-
-Example:
---------
-The following example demonstrates both a TI-SCI reset controller node and a
-consumer (a DSP device) on the 66AK2G SoC.
-
-pmmc: pmmc {
- compatible = "ti,k2g-sci";
-
- k2g_reset: reset-controller {
- compatible = "ti,sci-reset";
- #reset-cells = <2>;
- };
-};
-
-dsp0: dsp@10800000 {
- ...
- resets = <&k2g_reset 0x0046 0x1>;
- ...
-};
diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml
new file mode 100644
index 000000000000..4639d2cec557
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/ti,sci-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI reset controller node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This reset controller node uses the TI SCI protocol to perform the reset
+ management of various hardware modules present on the SoC. Must be a child
+ node of the associated TI-SCI system controller node.
+
+properties:
+ $nodename:
+ pattern: "^reset-controller$"
+
+ compatible:
+ const: ti,sci-reset
+
+ "#reset-cells":
+ const: 2
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell should contain the reset mask corresponding to the device
+ used by system controller.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+
+additionalProperties: false
+
+examples:
+ - |
+ k3_reset: reset-controller {
+ compatible = "ti,sci-reset";
+ #reset-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
index 23b227614366..1d38ff76d18f 100644
--- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml
@@ -56,7 +56,6 @@ properties:
interrupts:
minItems: 3
- maxItems: 4
items:
- description: DirError interrupt
- description: DataError interrupt
diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.txt b/Documentation/devicetree/bindings/rng/mtk-rng.txt
deleted file mode 100644
index dfdcb5cd2ea8..000000000000
--- a/Documentation/devicetree/bindings/rng/mtk-rng.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-Device-Tree bindings for Mediatek random number generator
-found in MediaTek SoC family
-
-Required properties:
-- compatible : Should be
- "mediatek,mt7622-rng", "mediatek,mt7623-rng" : for MT7622
- "mediatek,mt7629-rng", "mediatek,mt7623-rng" : for MT7629
- "mediatek,mt7623-rng" : for MT7623
- "mediatek,mt8516-rng", "mediatek,mt7623-rng" : for MT8516
-- clocks : list of clock specifiers, corresponding to
- entries in clock-names property;
-- clock-names : Should contain "rng" entries;
-- reg : Specifies base physical address and size of the registers
-
-Example:
-
-rng: rng@1020f000 {
- compatible = "mediatek,mt7623-rng";
- reg = <0 0x1020f000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_TRNG>;
- clock-names = "rng";
-};
diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
new file mode 100644
index 000000000000..61888e07bda0
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/mtk-rng.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: MediaTek Random number generator
+
+maintainers:
+ - Sean Wang <sean.wang@mediatek.com>
+
+properties:
+ $nodename:
+ pattern: "^rng@[0-9a-f]+$"
+
+ compatible:
+ oneOf:
+ - enum:
+ - mediatek,mt7623-rng
+ - items:
+ - enum:
+ - mediatek,mt7622-rng
+ - mediatek,mt7629-rng
+ - mediatek,mt8365-rng
+ - mediatek,mt8516-rng
+ - const: mediatek,mt7623-rng
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rng
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt2701-clk.h>
+ rng: rng@1020f000 {
+ compatible = "mediatek,mt7623-rng";
+ reg = <0x1020f000 0x1000>;
+ clocks = <&infracfg CLK_INFRA_TRNG>;
+ clock-names = "rng";
+ };
diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
index b1b0ee769b71..beeb90e55727 100644
--- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml
@@ -32,7 +32,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: RTC Alarm 0
- description: RTC Alarm 1
diff --git a/Documentation/devicetree/bindings/rtc/arm,pl031.yaml b/Documentation/devicetree/bindings/rtc/arm,pl031.yaml
new file mode 100644
index 000000000000..fa5f2eda372e
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/arm,pl031.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/arm,pl031.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Arm Primecell PL031 Real Time Clock
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: arm,pl031
+ required:
+ - compatible
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - const: arm,pl031
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ start-year: true
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@10017000 {
+ compatible = "arm,pl031", "arm,primecell";
+ reg = <0x10017000 0x1000>;
+ clocks = <&pclk>;
+ clock-names = "apb_pclk";
+ };
diff --git a/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
index 06bd737821c1..4807c95a663c 100644
--- a/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
+++ b/Documentation/devicetree/bindings/rtc/imxdi-rtc.yaml
@@ -21,7 +21,6 @@ properties:
- description: rtc alarm interrupt
- description: dryice security violation interrupt
minItems: 1
- maxItems: 2
clocks:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml
new file mode 100644
index 000000000000..a98b72752349
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/nxp,pcf8563.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/nxp,pcf8563.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Philips PCF8563/Epson RTC8564 Real Time Clock
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ enum:
+ - epson,rtc8564
+ - microcrystal,rv8564
+ - nxp,pca8565
+ - nxp,pcf8563
+ - nxp,pcf85263
+ - nxp,pcf85363
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 0
+
+ clock-output-names:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ start-year: true
+ wakeup-source: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ rtc@51 {
+ compatible = "nxp,pcf8563";
+ reg = <0x51>;
+ #clock-cells = <0>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/rtc/pcf85363.txt b/Documentation/devicetree/bindings/rtc/pcf85363.txt
deleted file mode 100644
index 94adc1cf93d9..000000000000
--- a/Documentation/devicetree/bindings/rtc/pcf85363.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-NXP PCF85263/PCF85363 Real Time Clock
-============================
-
-Required properties:
-- compatible: Should contain "nxp,pcf85263" or "nxp,pcf85363".
-- reg: I2C address for chip.
-
-Optional properties:
-- interrupts: IRQ line for the RTC (not implemented).
-
-Example:
-
-pcf85363: pcf85363@51 {
- compatible = "nxp,pcf85363";
- reg = <0x51>;
-};
-
diff --git a/Documentation/devicetree/bindings/rtc/pcf8563.txt b/Documentation/devicetree/bindings/rtc/pcf8563.txt
deleted file mode 100644
index 0a900f7c8977..000000000000
--- a/Documentation/devicetree/bindings/rtc/pcf8563.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-* Philips PCF8563/Epson RTC8564 Real Time Clock
-
-Philips PCF8563/Epson RTC8564 Real Time Clock
-
-Required properties:
-- compatible: Should contain "nxp,pcf8563",
- "epson,rtc8564" or
- "microcrystal,rv8564" or
- "nxp,pca8565"
-- reg: I2C address for chip.
-
-Optional property:
-- #clock-cells: Should be 0.
-- clock-output-names:
- overwrite the default clock name "pcf8563-clkout"
-
-Example:
-
-pcf8563: pcf8563@51 {
- compatible = "nxp,pcf8563";
- reg = <0x51>;
- #clock-cells = <0>;
-};
-
-device {
-...
- clocks = <&pcf8563>;
-...
-};
diff --git a/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
new file mode 100644
index 000000000000..bdb72d3ddf2a
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/xlnx,zynqmp-rtc.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/xlnx,zynqmp-rtc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
+
+description:
+ RTC controller for the Xilinx Zynq MPSoC Real Time Clock.
+ The RTC controller has separate IRQ lines for seconds and alarm.
+
+maintainers:
+ - Michal Simek <michal.simek@xilinx.com>
+
+allOf:
+ - $ref: rtc.yaml#
+
+properties:
+ compatible:
+ const: xlnx,zynqmp-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+
+ interrupt-names:
+ items:
+ - const: alarm
+ - const: sec
+
+ calibration:
+ description: |
+ calibration value for 1 sec period which will
+ be programmed directly to calibration register.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 0x1
+ maximum: 0x1FFFFF
+ default: 0x198233
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ rtc: rtc@ffa60000 {
+ compatible = "xlnx,zynqmp-rtc";
+ reg = <0x0 0xffa60000 0x0 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 26 4>, <0 27 4>;
+ interrupt-names = "alarm", "sec";
+ calibration = <0x198233>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt b/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
deleted file mode 100644
index 0df6f016b1b7..000000000000
--- a/Documentation/devicetree/bindings/rtc/xlnx-rtc.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock
-
-RTC controller for the Xilinx Zynq MPSoC Real Time Clock
-Separate IRQ lines for seconds and alarm
-
-Required properties:
-- compatible: Should be "xlnx,zynqmp-rtc"
-- reg: Physical base address of the controller and length
- of memory mapped region.
-- interrupts: IRQ lines for the RTC.
-- interrupt-names: interrupt line names eg. "sec" "alarm"
-
-Optional:
-- calibration: calibration value for 1 sec period which will
- be programmed directly to calibration register
-
-Example:
-rtc: rtc@ffa60000 {
- compatible = "xlnx,zynqmp-rtc";
- reg = <0x0 0xffa60000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 26 4>, <0 27 4>;
- interrupt-names = "alarm", "sec";
- calibration = <0x198233>;
-};
diff --git a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
index bd21060d26e0..a90c971b4f1f 100644
--- a/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl-lpuart.yaml
@@ -36,14 +36,12 @@ properties:
- description: ipg clock
- description: baud clock
minItems: 1
- maxItems: 2
clock-names:
items:
- const: ipg
- const: baud
minItems: 1
- maxItems: 2
dmas:
items:
diff --git a/Documentation/devicetree/bindings/serial/samsung_uart.yaml b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
index 97ec8a093bf3..3ec3822bd114 100644
--- a/Documentation/devicetree/bindings/serial/samsung_uart.yaml
+++ b/Documentation/devicetree/bindings/serial/samsung_uart.yaml
@@ -44,7 +44,6 @@ properties:
clock-names:
description: N = 0 is allowed for SoCs without internal baud clock mux.
minItems: 2
- maxItems: 5
items:
- const: uart
- pattern: '^clk_uart_baud[0-3]$'
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
index 84671950ca0d..4663c2bcad50 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml
@@ -164,7 +164,6 @@ patternProperties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: UART core irq
- description: Wakeup irq (RX GPIO)
diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
deleted file mode 100644
index 6217e64309de..000000000000
--- a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+++ /dev/null
@@ -1,65 +0,0 @@
-Texas Instruments TI-SCI Generic Power Domain
----------------------------------------------
-
-Some TI SoCs contain a system controller (like the PMMC, etc...) that is
-responsible for controlling the state of the IPs that are present.
-Communication between the host processor running an OS and the system
-controller happens through a protocol known as TI-SCI [1].
-
-[1] Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
-
-PM Domain Node
-==============
-The PM domain node represents the global PM domain managed by the PMMC, which
-in this case is the implementation as documented by the generic PM domain
-bindings in Documentation/devicetree/bindings/power/power-domain.yaml. Because
-this relies on the TI SCI protocol to communicate with the PMMC it must be a
-child of the pmmc node.
-
-Required Properties:
---------------------
-- compatible: should be "ti,sci-pm-domain"
-- #power-domain-cells: Can be one of the following:
- 1: Containing the device id of each node
- 2: First entry should be device id
- Second entry should be one of the floowing:
- TI_SCI_PD_EXCLUSIVE: To allow device to be
- exclusively controlled by
- the requesting hosts.
- TI_SCI_PD_SHARED: To allow device to be shared
- by multiple hosts.
-
-Example (K2G):
--------------
- pmmc: pmmc {
- compatible = "ti,k2g-sci";
- ...
-
- k2g_pds: power-controller {
- compatible = "ti,sci-pm-domain";
- #power-domain-cells = <1>;
- };
- };
-
-PM Domain Consumers
-===================
-Hardware blocks belonging to a PM domain should contain a "power-domains"
-property that is a phandle pointing to the corresponding PM domain node
-along with an index representing the device id to be passed to the PMMC
-for device control.
-
-Required Properties:
---------------------
-- power-domains: phandle pointing to the corresponding PM domain node
- and an ID representing the device.
-
-See http://processors.wiki.ti.com/index.php/TISCI#66AK2G02_Data for the list
-of valid identifiers for k2g.
-
-Example (K2G):
---------------------
- uart0: serial@2530c00 {
- compatible = "ns16550a";
- ...
- power-domains = <&k2g_pds 0x002c>;
- };
diff --git a/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
new file mode 100644
index 000000000000..9e6cb4ee9755
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/ti/sci-pm-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI-SCI generic power domain node bindings
+
+maintainers:
+ - Nishanth Menon <nm@ti.com>
+
+allOf:
+ - $ref: /schemas/power/power-domain.yaml#
+
+description: |
+ Some TI SoCs contain a system controller (like the Power Management Micro
+ Controller (PMMC) on Keystone 66AK2G SoC) that are responsible for controlling
+ the state of the various hardware modules present on the SoC. Communication
+ between the host processor running an OS and the system controller happens
+ through a protocol called TI System Control Interface (TI-SCI protocol).
+
+ This PM domain node represents the global PM domain managed by the TI-SCI
+ controller. Since this relies on the TI SCI protocol to communicate with
+ the TI-SCI controller, it must be a child of the TI-SCI controller node.
+
+properties:
+ compatible:
+ const: ti,sci-pm-domain
+
+ "#power-domain-cells":
+ enum: [1, 2]
+ description:
+ The two cells represent values that the TI-SCI controller defines.
+
+ The first cell should contain the device ID.
+
+ The second cell, if cell-value is 2, should be one of the following
+ TI_SCI_PD_EXCLUSIVE - Allows the device to be exclusively controlled
+ or
+ TI_SCI_PD_SHARED - Allows the device to be shared by multiple hosts.
+ Please refer to dt-bindings/soc/ti,sci_pm_domain.h for the definitions.
+
+ Please see http://processors.wiki.ti.com/index.php/TISCI for
+ protocol documentation for the values to be used for different devices.
+
+additionalProperties: false
+
+examples:
+ - |
+ k2g_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <1>;
+ };
+
+ - |
+ k3_pds: power-controller {
+ compatible = "ti,sci-pm-domain";
+ #power-domain-cells = <2>;
+ };
diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
index dbc62821c60b..9790617af1bc 100644
--- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
+++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml
@@ -100,7 +100,6 @@ patternProperties:
properties:
reg:
minItems: 2 # On AM437x one of two PRUSS units don't contain Shared RAM.
- maxItems: 3
items:
- description: Address and size of the Data RAM0.
- description: Address and size of the Data RAM1.
@@ -111,7 +110,6 @@ patternProperties:
reg-names:
minItems: 2
- maxItems: 3
items:
- const: dram0
- const: dram1
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml
index 249970952202..5bdd30a8a404 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml
@@ -28,7 +28,6 @@ properties:
minItems: 2
clock-names:
- minItems: 2
items:
- const: pll_a
- const: plla_out0
diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
index 38e52e7dbb40..63370709c768 100644
--- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
+++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-i2s.yaml
@@ -34,7 +34,6 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: I2S bit clock
- description:
@@ -48,7 +47,6 @@ properties:
clock-names:
minItems: 1
- maxItems: 2
items:
- const: i2s
- const: sync_input
diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
index f2443b651282..06e83461705c 100644
--- a/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
+++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.yaml
@@ -26,7 +26,6 @@ properties:
- description: Base address and size of SAI common register set.
- description: Base address and size of SAI identification register set.
minItems: 1
- maxItems: 2
ranges:
maxItems: 1
@@ -81,14 +80,12 @@ patternProperties:
- description: sai_ck clock feeding the internal clock generator.
- description: MCLK clock from a SAI set as master clock provider.
minItems: 1
- maxItems: 2
clock-names:
items:
- const: sai_ck
- const: MCLK
minItems: 1
- maxItems: 2
dmas:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
index e3fb553d9180..4d46c49ec32b 100644
--- a/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
+++ b/Documentation/devicetree/bindings/spi/amlogic,meson-gx-spicc.yaml
@@ -35,7 +35,6 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: controller register bus clock
- description: baud rate generator and delay control clock
diff --git a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
index 6ee19d49fd3c..ec5873919170 100644
--- a/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.yaml
@@ -56,7 +56,6 @@ properties:
reg-names:
minItems: 1
- maxItems: 5
items:
- const: mspi
- const: bspi
@@ -71,7 +70,6 @@ properties:
interrupt-names:
oneOf:
- minItems: 1
- maxItems: 7
items:
- const: mspi_done
- const: mspi_halted
diff --git a/Documentation/devicetree/bindings/spi/spi-davinci.txt b/Documentation/devicetree/bindings/spi/spi-davinci.txt
index e2198a389484..200c7fc7b089 100644
--- a/Documentation/devicetree/bindings/spi/spi-davinci.txt
+++ b/Documentation/devicetree/bindings/spi/spi-davinci.txt
@@ -25,7 +25,7 @@ Required properties:
- interrupts: interrupt number mapped to CPU.
- clocks: spi clk phandle
For 66AK2G this property should be set per binding,
- Documentation/devicetree/bindings/clock/ti,sci-clk.txt
+ Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
SoC-specific Required Properties:
diff --git a/Documentation/devicetree/bindings/spmi/spmi.yaml b/Documentation/devicetree/bindings/spmi/spmi.yaml
index 173940930719..1d243faef2f8 100644
--- a/Documentation/devicetree/bindings/spmi/spmi.yaml
+++ b/Documentation/devicetree/bindings/spmi/spmi.yaml
@@ -40,14 +40,15 @@ patternProperties:
properties:
reg:
- minItems: 1
- maxItems: 2
items:
- - minimum: 0
- maximum: 0xf
- - enum: [ 0 ]
- description: |
- 0 means user ID address. 1 is reserved for group ID address.
+ - minItems: 1
+ items:
+ - minimum: 0
+ maximum: 0xf
+ - enum: [ 0 ]
+ description:
+ 0 means user ID address. 1 is reserved for group ID
+ address.
required:
- reg
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index c1a5afa73cfe..3eda5049d183 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -28,6 +28,8 @@ properties:
contains:
enum:
- mmio-sram
+ - amlogic,meson-gxbb-sram
+ - arm,juno-sram-ns
- atmel,sama5d2-securam
- rockchip,rk3288-pmu-sram
@@ -80,6 +82,9 @@ patternProperties:
- amlogic,meson8b-smp-sram
- amlogic,meson-gxbb-scp-shmem
- amlogic,meson-axg-scp-shmem
+ - arm,juno-scp-shmem
+ - arm,scmi-shmem
+ - arm,scp-shmem
- renesas,smp-sram
- rockchip,rk3066-smp-sram
- samsung,exynos4210-sysram
diff --git a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
index bf97d1fb33e7..6e0b110153b0 100644
--- a/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
+++ b/Documentation/devicetree/bindings/thermal/allwinner,sun8i-a83t-ths.yaml
@@ -23,14 +23,12 @@ properties:
clocks:
minItems: 1
- maxItems: 2
items:
- description: Bus Clock
- description: Module Clock
clock-names:
minItems: 1
- maxItems: 2
items:
- const: bus
- const: mod
diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
index 0242fd91b622..0b3b6af7bd5b 100644
--- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
+++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml
@@ -77,7 +77,6 @@ properties:
nvmem-cell-names:
minItems: 1
- maxItems: 2
items:
- const: calib
- enum:
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
index b6a6d03a08b2..2ecac754e1cd 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml
@@ -24,7 +24,6 @@ properties:
interrupts:
minItems: 2
- maxItems: 4
items:
- description: Timer 0 Interrupt
- description: Timer 1 Interrupt
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
index 7f5e3af58255..df8ce87fd54b 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -35,7 +35,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 5
items:
- description: secure timer irq
- description: non-secure timer irq
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
index d83a1f97f911..cd2176cad53a 100644
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
@@ -71,14 +71,12 @@ patternProperties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: physical timer irq
- description: virtual timer irq
reg:
minItems: 1
- maxItems: 2
items:
- description: 1st view base address
- description: 2nd optional view base address
diff --git a/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml
new file mode 100644
index 000000000000..5684df6448ef
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,twd-timer.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,twd-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Timer-Watchdog Timer
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
+ Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
+ and watchdog.
+
+ The TWD is usually attached to a GIC to deliver its two per-processor
+ interrupts.
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-twd-timer
+ - arm,cortex-a5-twd-timer
+ - arm,arm11mp-twd-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ always-on:
+ description:
+ If present, the timer is powered through an always-on power domain,
+ therefore it never loses context.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ timer@2c000600 {
+ compatible = "arm,arm11mp-twd-timer";
+ reg = <0x2c000600 0x20>;
+ interrupts = <GIC_PPI 13 0xf01>;
+ };
diff --git a/Documentation/devicetree/bindings/timer/arm,twd.txt b/Documentation/devicetree/bindings/timer/arm,twd.txt
deleted file mode 100644
index 383ea19c2bf0..000000000000
--- a/Documentation/devicetree/bindings/timer/arm,twd.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-* ARM Timer Watchdog
-
-ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
-Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
-and watchdog.
-
-The TWD is usually attached to a GIC to deliver its two per-processor
-interrupts.
-
-** Timer node required properties:
-
-- compatible : Should be one of:
- "arm,cortex-a9-twd-timer"
- "arm,cortex-a5-twd-timer"
- "arm,arm11mp-twd-timer"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD timer
- register window.
-
-Optional
-
-- always-on : a boolean property. If present, the timer is powered through
- an always-on power domain, therefore it never loses context.
-
-Example:
-
- twd-timer@2c000600 {
- compatible = "arm,arm11mp-twd-timer"";
- reg = <0x2c000600 0x20>;
- interrupts = <1 13 0xf01>;
- };
-
-** Watchdog node properties:
-
-- compatible : Should be one of:
- "arm,cortex-a9-twd-wdt"
- "arm,cortex-a5-twd-wdt"
- "arm,arm11mp-twd-wdt"
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the TWD watchdog
- register window.
-
-Example:
-
- twd-watchdog@2c000620 {
- compatible = "arm,arm11mp-twd-wdt";
- reg = <0x2c000620 0x20>;
- interrupts = <1 14 0xf01>;
- };
diff --git a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
index a8de99b0c0f9..f32575d4b5aa 100644
--- a/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
+++ b/Documentation/devicetree/bindings/timer/intel,ixp4xx-timer.yaml
@@ -22,7 +22,6 @@ properties:
interrupts:
minItems: 1
- maxItems: 2
items:
- description: Timer 1 interrupt
- description: Timer 2 interrupt
diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
index f0f0f121c355..c57169118b68 100644
--- a/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,tmu.yaml
@@ -36,6 +36,7 @@ properties:
- renesas,tmu-r8a77980 # R-Car V3H
- renesas,tmu-r8a77990 # R-Car E3
- renesas,tmu-r8a77995 # R-Car D3
+ - renesas,tmu-r8a779a0 # R-Car V3U
- const: renesas,tmu
reg:
diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.txt b/Documentation/devicetree/bindings/timer/renesas,tpu.txt
deleted file mode 100644
index 1d46f9de4feb..000000000000
--- a/Documentation/devicetree/bindings/timer/renesas,tpu.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-* Renesas H8/300 Timer Pulse Unit
-
-The TPU is a 16bit timer/counter with configurable clock inputs and
-programmable compare match.
-This implementation support only cascade mode.
-
-Required Properties:
-
- - compatible: must contain "renesas,tpu"
- - reg: base address and length of the registers block in 2 channel.
- - clocks: a list of phandle, one for each entry in clock-names.
- - clock-names: must contain "peripheral_clk" for the functional clock.
-
-
-Example:
- tpu: tpu@ffffe0 {
- compatible = "renesas,tpu";
- reg = <0xffffe0 16>, <0xfffff0 12>;
- clocks = <&pclk>;
- clock-names = "peripheral_clk";
- };
diff --git a/Documentation/devicetree/bindings/timer/renesas,tpu.yaml b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml
new file mode 100644
index 000000000000..01554dff23d8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/renesas,tpu.yaml
@@ -0,0 +1,56 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/renesas,tpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Renesas H8/300 Timer Pulse Unit
+
+maintainers:
+ - Yoshinori Sato <ysato@users.sourceforge.jp>
+
+description:
+ The TPU is a 16bit timer/counter with configurable clock inputs and
+ programmable compare match.
+ This implementation supports only cascade mode.
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: renesas,tpu
+ '#pwm-cells': false
+ required:
+ - compatible
+
+properties:
+ compatible:
+ const: renesas,tpu
+
+ reg:
+ items:
+ - description: First channel
+ - description: Second channel
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: fck
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ tpu: tpu@ffffe0 {
+ compatible = "renesas,tpu";
+ reg = <0xffffe0 16>, <0xfffff0 12>;
+ clocks = <&pclk>;
+ clock-names = "fck";
+ };
diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml
index a407e1143cf4..8dedfa16c992 100644
--- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml
+++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml
@@ -28,9 +28,9 @@ properties:
interrupts:
minItems: 3
items:
- - description: OTG/DRD controller interrupt
- description: XHCI host controller interrupt
- description: Device controller interrupt
+ - description: OTG/DRD controller interrupt
- description: interrupt used to wake up core, e.g when usbcmd.rs is
cleared by xhci core, this interrupt is optional
diff --git a/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml b/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml
index 4241d38d5864..1d893d3d3432 100644
--- a/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml
+++ b/Documentation/devicetree/bindings/usb/maxim,max3420-udc.yaml
@@ -30,14 +30,12 @@ properties:
- description: usb irq from max3420
- description: vbus detection irq
minItems: 1
- maxItems: 2
interrupt-names:
items:
- const: udc
- const: vbus
minItems: 1
- maxItems: 2
spi-max-frequency:
maximum: 26000000
diff --git a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml
index e60e590dbe12..8428415896ce 100644
--- a/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml
+++ b/Documentation/devicetree/bindings/usb/nvidia,tegra-xudc.yaml
@@ -25,7 +25,6 @@ properties:
reg:
minItems: 2
- maxItems: 3
items:
- description: XUSB device controller registers
- description: XUSB device PCI Config registers
@@ -33,7 +32,6 @@ properties:
reg-names:
minItems: 2
- maxItems: 3
items:
- const: base
- const: fpci
@@ -45,7 +43,6 @@ properties:
clocks:
minItems: 4
- maxItems: 5
items:
- description: Clock to enable core XUSB dev clock.
- description: Clock to enable XUSB super speed clock.
@@ -55,7 +52,6 @@ properties:
clock-names:
minItems: 4
- maxItems: 5
items:
- const: dev
- const: ss
diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
index e67223d90bb7..ad73339ffe1d 100644
--- a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
+++ b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
@@ -53,7 +53,6 @@ properties:
clocks:
minItems: 1
- maxItems: 3
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
@@ -86,7 +85,6 @@ properties:
dma-names:
minItems: 2
- maxItems: 4
items:
- const: ch0
- const: ch1
@@ -100,7 +98,6 @@ properties:
resets:
minItems: 1
- maxItems: 2
items:
- description: USB 2.0 host
- description: USB 2.0 peripheral
diff --git a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml
index 7ec87a783c5c..a634774c537c 100644
--- a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml
+++ b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml
@@ -27,7 +27,7 @@ properties:
description:
PM domain provider node and an args specifier containing
the USB device id value. See,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
maxItems: 1
clocks:
diff --git a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
index 9a068d3bc73b..f6e91a5fd8fe 100644
--- a/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/ti,keystone-dwc3.yaml
@@ -47,7 +47,7 @@ properties:
description: Should contain a phandle to a PM domain provider node
and an args specifier containing the USB device id
value. This property is as per the binding,
- Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
+ Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
phys:
maxItems: 1
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 9cb628ec960b..f25a1fbf8175 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -472,7 +472,7 @@ patternProperties:
"^hirschmann,.*":
description: Hirschmann Automation and Control GmbH
"^hisilicon,.*":
- description: Hisilicon Limited.
+ description: HiSilicon Limited.
"^hit,.*":
description: Hitachi Ltd.
"^hitex,.*":
@@ -533,6 +533,8 @@ patternProperties:
description: Innolux Corporation
"^inside-secure,.*":
description: INSIDE Secure
+ "^insignal,.*":
+ description: Insignal Ltd.
"^inspur,.*":
description: Inspur Corporation
"^intel,.*":
@@ -1087,6 +1089,8 @@ patternProperties:
(formerly part of MStar Semiconductor, Inc.)
"^st,.*":
description: STMicroelectronics
+ "^starfive,.*":
+ description: StarFive Technology Co. Ltd.
"^starry,.*":
description: Starry Electronic Technology (ShenZhen) Co., LTD
"^startek,.*":
diff --git a/Documentation/devicetree/bindings/virtio/mmio.txt b/Documentation/devicetree/bindings/virtio/mmio.txt
deleted file mode 100644
index 0a575f329f6e..000000000000
--- a/Documentation/devicetree/bindings/virtio/mmio.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-* virtio memory mapped device
-
-See https://ozlabs.org/~rusty/virtio-spec/ for more details.
-
-Required properties:
-
-- compatible: "virtio,mmio" compatibility string
-- reg: control registers base address and size including configuration space
-- interrupts: interrupt generated by the device
-
-Required properties for virtio-iommu:
-
-- #iommu-cells: When the node corresponds to a virtio-iommu device, it is
- linked to DMA masters using the "iommus" or "iommu-map"
- properties [1][2]. #iommu-cells specifies the size of the
- "iommus" property. For virtio-iommu #iommu-cells must be
- 1, each cell describing a single endpoint ID.
-
-Optional properties:
-
-- iommus: If the device accesses memory through an IOMMU, it should
- have an "iommus" property [1]. Since virtio-iommu itself
- does not access memory through an IOMMU, the "virtio,mmio"
- node cannot have both an "#iommu-cells" and an "iommus"
- property.
-
-Example:
-
- virtio_block@3000 {
- compatible = "virtio,mmio";
- reg = <0x3000 0x100>;
- interrupts = <41>;
-
- /* Device has endpoint ID 23 */
- iommus = <&viommu 23>
- }
-
- viommu: iommu@3100 {
- compatible = "virtio,mmio";
- reg = <0x3100 0x100>;
- interrupts = <42>;
-
- #iommu-cells = <1>
- }
-
-[1] Documentation/devicetree/bindings/iommu/iommu.txt
-[2] Documentation/devicetree/bindings/pci/pci-iommu.txt
diff --git a/Documentation/devicetree/bindings/virtio/mmio.yaml b/Documentation/devicetree/bindings/virtio/mmio.yaml
new file mode 100644
index 000000000000..d46597028cf1
--- /dev/null
+++ b/Documentation/devicetree/bindings/virtio/mmio.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/virtio/mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: virtio memory mapped devices
+
+maintainers:
+ - Jean-Philippe Brucker <jean-philippe@linaro.org>
+
+description:
+ See https://www.oasis-open.org/committees/tc_home.php?wg_abbrev=virtio for
+ more details.
+
+properties:
+ compatible:
+ const: virtio,mmio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#iommu-cells':
+ description: Required when the node corresponds to a virtio-iommu device.
+ const: 1
+
+ iommus:
+ description: Required for devices making accesses thru an IOMMU.
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ virtio@3000 {
+ compatible = "virtio,mmio";
+ reg = <0x3000 0x100>;
+ interrupts = <41>;
+
+ /* Device has endpoint ID 23 */
+ iommus = <&viommu 23>;
+ };
+
+ viommu: iommu@3100 {
+ compatible = "virtio,mmio";
+ reg = <0x3100 0x100>;
+ interrupts = <42>;
+
+ #iommu-cells = <1>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml b/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml
new file mode 100644
index 000000000000..6bfa46353c4e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/arm,sbsa-gwdt.yaml
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/arm,sbsa-gwdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SBSA (Server Base System Architecture) Generic Watchdog
+
+maintainers:
+ - Fu Wei <fu.wei@linaro.org>
+
+description: |
+ The SBSA Generic Watchdog Timer is used to force a reset of the system after
+ two stages of timeout have elapsed. A detailed definition of the watchdog
+ timer can be found in the ARM document: ARM-DEN-0029 - Server Base System
+ Architecture (SBSA)
+
+allOf:
+ - $ref: watchdog.yaml#
+
+properties:
+ compatible:
+ const: arm,sbsa-gwdt
+
+ reg:
+ items:
+ - description: Watchdog control frame
+ - description: Refresh frame
+
+ interrupts:
+ description: The Watchdog Signal 0 (WS0) SPI (Shared Peripheral Interrupt)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+
+ watchdog@2a440000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x2a440000 0x1000>,
+ <0x2a450000 0x1000>;
+ interrupts = <0 27 4>;
+ timeout-sec = <30>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml b/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml
new file mode 100644
index 000000000000..bb8901854222
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/arm,twd-wdt.yaml
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/watchdog/arm,twd-wdt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Timer-Watchdog Watchdog
+
+maintainers:
+ - Rob Herring <robh@kernel.org>
+
+description:
+ ARM 11MP, Cortex-A5 and Cortex-A9 are often associated with a per-core
+ Timer-Watchdog (aka TWD), which provides both a per-cpu local timer
+ and watchdog.
+
+ The TWD is usually attached to a GIC to deliver its two per-processor
+ interrupts.
+
+properties:
+ compatible:
+ enum:
+ - arm,cortex-a9-twd-wdt
+ - arm,cortex-a5-twd-wdt
+ - arm,arm11mp-twd-wdt
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ watchdog@2c000620 {
+ compatible = "arm,arm11mp-twd-wdt";
+ reg = <0x2c000620 0x20>;
+ interrupts = <GIC_PPI 14 0xf01>;
+ };
diff --git a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt b/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
deleted file mode 100644
index 6f2d5f91964d..000000000000
--- a/Documentation/devicetree/bindings/watchdog/sbsa-gwdt.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-* SBSA (Server Base System Architecture) Generic Watchdog
-
-The SBSA Generic Watchdog Timer is used to force a reset of the system
-after two stages of timeout have elapsed. A detailed definition of the
-watchdog timer can be found in the ARM document: ARM-DEN-0029 - Server
-Base System Architecture (SBSA)
-
-Required properties:
-- compatible: Should at least contain "arm,sbsa-gwdt".
-
-- reg: Each entry specifies the base physical address of a register frame
- and the length of that frame; currently, two frames must be defined,
- in this order:
- 1: Watchdog control frame;
- 2: Refresh frame.
-
-- interrupts: Should contain the Watchdog Signal 0 (WS0) SPI (Shared
- Peripheral Interrupt) number of SBSA Generic Watchdog.
-
-Optional properties
-- timeout-sec: Watchdog timeout values (in seconds).
-
-Example for FVP Foundation Model v8:
-
-watchdog@2a440000 {
- compatible = "arm,sbsa-gwdt";
- reg = <0x0 0x2a440000 0 0x1000>,
- <0x0 0x2a450000 0 0x1000>;
- interrupts = <0 27 4>;
- timeout-sec = <30>;
-};
diff --git a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
index 3f1ba1d6c6b5..481bf91f988a 100644
--- a/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
+++ b/Documentation/devicetree/bindings/watchdog/st,stm32-iwdg.yaml
@@ -27,7 +27,6 @@ properties:
- description: Low speed clock
- description: Optional peripheral clock
minItems: 1
- maxItems: 2
clock-names:
items:
diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst
index 45ff426d0019..f7dfb98c156e 100644
--- a/Documentation/devicetree/bindings/writing-bindings.rst
+++ b/Documentation/devicetree/bindings/writing-bindings.rst
@@ -52,7 +52,8 @@ Properties
constraints specific to the device.
- DO use common property unit suffixes for properties with scientific units.
- See property-units.txt.
+ Recommended suffixes are listed at
+ https://github.com/devicetree-org/dt-schema/blob/master/schemas/property-units.yaml
- DO define properties in terms of constraints. How many entries? What are
possible values? What is the order?