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authorPalmer Dabbelt <palmer@rivosinc.com>2023-08-16 07:28:26 -0700
committerPalmer Dabbelt <palmer@rivosinc.com>2023-08-23 09:07:28 -0700
commit7aa7d502e4d5a42353325cb4bf2aa880b10168e9 (patch)
treebe8c3acd23298081b6a3085c0a7e1b2b36a48656 /Documentation
parent9f944d2e0ab39296bfadb29167dc333815ba9f48 (diff)
parent26ba042414a35cb1fd7c31fae63841956ce7cecb (diff)
Merge patch series "riscv: Allow userspace to directly access perf counters"
Alexandre Ghiti <alexghiti@rivosinc.com> says: riscv used to allow direct access to cycle/time/instret counters, bypassing the perf framework, this patchset intends to allow the user to mmap any counter when accessed through perf. **Important**: The default mode is now user access through perf only, not the legacy so some applications will break. However, we introduce a sysctl perf_user_access like arm64 does, which will allow to switch to the legacy mode described above. This version needs openSBI v1.3 *and* a kernel fix that went upstream lately (https://lore.kernel.org/lkml/20230616114831.3186980-1-maz@kernel.org/T/). * b4-shazam-merge: perf: tests: Adapt mmap-basic.c for riscv tools: lib: perf: Implement riscv mmap support Documentation: admin-guide: Add riscv sysctl_perf_user_access drivers: perf: Implement perf event mmap support in the SBI backend drivers: perf: Implement perf event mmap support in the legacy backend riscv: Prepare for user-space perf event mmap support drivers: perf: Rename riscv pmu sbi driver riscv: Make legacy counter enum match the HW numbering include: riscv: Fix wrong include guard in riscv_pmu.h perf: Fix wrong comment about default event_idx Link: https://lore.kernel.org/r/20230802080328.1213905-1-alexghiti@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/admin-guide/sysctl/kernel.rst27
1 files changed, 23 insertions, 4 deletions
diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst
index 3800fab1619b..8019103aac10 100644
--- a/Documentation/admin-guide/sysctl/kernel.rst
+++ b/Documentation/admin-guide/sysctl/kernel.rst
@@ -941,16 +941,35 @@ enabled, otherwise writing to this file will return ``-EBUSY``.
The default value is 8.
-perf_user_access (arm64 only)
-=================================
+perf_user_access (arm64 and riscv only)
+=======================================
+
+Controls user space access for reading perf event counters.
-Controls user space access for reading perf event counters. When set to 1,
-user space can read performance monitor counter registers directly.
+arm64
+=====
The default value is 0 (access disabled).
+When set to 1, user space can read performance monitor counter registers
+directly.
+
See Documentation/arch/arm64/perf.rst for more information.
+riscv
+=====
+
+When set to 0, user space access is disabled.
+
+The default value is 1, user space can read performance monitor counter
+registers through perf, any direct access without perf intervention will trigger
+an illegal instruction.
+
+When set to 2, which enables legacy mode (user space has direct access to cycle
+and insret CSRs only). Note that this legacy value is deprecated and will be
+removed once all user space applications are fixed.
+
+Note that the time CSR is always directly accessible to all modes.
pid_max
=======