diff options
| author | Ard Biesheuvel <ard.biesheuvel@linaro.org> | 2017-10-17 17:55:56 +0100 |
|---|---|---|
| committer | Marc Zyngier <marc.zyngier@arm.com> | 2017-10-19 11:22:39 +0100 |
| commit | 558b01654d92332d3b7b17bf773cdce8ce16ef46 (patch) | |
| tree | 52c1a98cbd4cc0e950801328a92404ce6db85b50 /Documentation | |
| parent | 9d111d49106b61f5a652d5418e85d8741b1a0427 (diff) | |
irqchip/gic-v3: Add workaround for Synquacer pre-ITS
The Socionext Synquacer SoC's implementation of GICv3 has a so-called
'pre-ITS', which maps 32-bit writes targeted at a separate window of
size '4 << device_id_bits' onto writes to GITS_TRANSLATER with device
ID taken from bits [device_id_bits + 1:2] of the window offset.
Writes that target GITS_TRANSLATER directly are reported as originating
from device ID #0.
So add a workaround for this. Given that this breaks isolation, clear
the IRQ_DOMAIN_FLAG_MSI_REMAP flag as well.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt index 4c29cdab0ea5..c3e6092f3add 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt @@ -75,6 +75,10 @@ These nodes must have the following properties: - reg: Specifies the base physical address and size of the ITS registers. +Optional: +- socionext,synquacer-pre-its: (u32, u32) tuple describing the untranslated + address and size of the pre-ITS window. + The main GIC node must contain the appropriate #address-cells, #size-cells and ranges properties for the reg property of all ITS nodes. |