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authorBjarni Jonasson <bjarni.jonasson@microchip.com>2021-01-13 12:56:25 +0100
committerJakub Kicinski <kuba@kernel.org>2021-01-14 15:40:33 -0800
commitb1ae3587d16a8c8fc9453e147c8708d6f006ffbb (patch)
tree691015386513e94a7b17948acbcbbc4948a0bcd1 /Documentation
parent3c51fa5d2afe7a4909b53af5019635326389dd29 (diff)
net: phy: Add 100 base-x mode
Sparx-5 supports this mode and it is missing in the PHY core. Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Reviewed-by: Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/networking/phy.rst5
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
index b2f7ec794bc8..399f17976a6c 100644
--- a/Documentation/networking/phy.rst
+++ b/Documentation/networking/phy.rst
@@ -286,6 +286,11 @@ Some of the interface modes are described below:
Note: due to legacy usage, some 10GBASE-R usage incorrectly makes
use of this definition.
+``PHY_INTERFACE_MODE_100BASEX``
+ This defines IEEE 802.3 Clause 24. The link operates at a fixed data
+ rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
+ data rate of 100Mpbs.
+
Pause frames / flow control
===========================