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authorLinus Torvalds <torvalds@linux-foundation.org>2015-06-23 13:34:02 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2015-06-23 13:34:02 -0700
commit10b4b096d0c7e9f1b5f84c2a0658b2963e1e6ed0 (patch)
tree5fce399661c128dddc2668ab1ffdb3f66c4f4e3f /Documentation
parentc70c5fb2b96dae0996fb0877d996458d3ca57eda (diff)
parent38e003f4b5dc405158b9ce625d8cc2b336d45497 (diff)
Merge tag 'gpio-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull gpio updates from Linus Walleij: "This is the big bulk of GPIO changes queued for the v4.2 kernel series: - a big set of cleanups to the aged sysfs interface from Johan Hovold. To get these in, v4.1-rc3 was merged into the tree as the first patch in that series had to go into stable. This makes the locking much more fine-grained (get rid of the "big GPIO lock(s)" and store states in the GPIO descriptors. - rename gpiod_[g|s]et_array() to gpiod_[g|s]et_array_value() to avoid confusions. - New drivers for: * NXP LPC18xx (currently LPC1850) * NetLogic XLP * Broadcom STB SoC's * Axis ETRAXFS * Zynq Ultrascale+ (subdriver) - ACPI: * make it possible to retrieve GpioInt resources from a GPIO device using acpi_dev_gpio_irq_get() * merge some dependent I2C changes exploiting this. * support the ARM X-Gene GPIO standby driver. - make it possible for the generic GPIO driver to read back the value set registers to reflect current status. - loads of OMAP IRQ handling fixes. - incremental improvements to Kona, max732x, OMAP, MXC, RCAR, PCA953x, STP-XWAY, PCF857x, Crystalcove, TB10x. - janitorial (constification, checkpatch cleanups)" * tag 'gpio-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (71 commits) gpio: Fix checkpatch.pl issues gpio: pcf857x: handle only enabled irqs gpio / ACPI: Return -EPROBE_DEFER if the gpiochip was not found GPIO / ACPI: export acpi_gpiochip_request(free)_interrupts for module use gpio: improve error reporting on own descriptors gpio: promote own request failure to pr_err() gpio: Added support to Zynq Ultrascale+ MPSoC gpio: add ETRAXFS GPIO driver fix documentation after renaming gpiod_set_array to gpiod_set_array_value gpio: Add GPIO support for Broadcom STB SoCs gpio: xgene: add ACPI support for APM X-Gene GPIO standby driver gpio: tb10x: Drop unneeded free_irq() call gpio: crystalcove: set IRQCHIP_SKIP_SET_WAKE for the irqchip gpio: stp-xway: Use the of_property_read_u32 helper gpio: pcf857x: Check for irq_set_irq_wake() failures gpio-stp-xway: Fix enabling the highest bit of the PHY LEDs gpio: Prevent an integer overflow in the pca953x driver gpio: omap: rework omap_gpio_irq_startup to handle current pin state properly gpio: omap: rework omap_gpio_request to touch only gpio specific registers gpio: omap: rework omap_x_irq_shutdown to touch only irqs specific registers ...
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt65
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt21
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-xlp.txt47
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio-zynq.txt2
-rw-r--r--Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt39
-rw-r--r--Documentation/gpio/consumer.txt28
-rw-r--r--Documentation/gpio/gpio-legacy.txt9
-rw-r--r--Documentation/gpio/sysfs.txt8
-rw-r--r--Documentation/zh_CN/gpio.txt8
9 files changed, 187 insertions, 40 deletions
diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
new file mode 100644
index 000000000000..435f1bcca341
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
@@ -0,0 +1,65 @@
+Broadcom STB "UPG GIO" GPIO controller
+
+The controller's registers are organized as sets of eight 32-bit
+registers with each set controlling a bank of up to 32 pins. A single
+interrupt is shared for all of the banks handled by the controller.
+
+Required properties:
+
+- compatible:
+ Must be "brcm,brcmstb-gpio"
+
+- reg:
+ Define the base and range of the I/O address space containing
+ the brcmstb GPIO controller registers
+
+- #gpio-cells:
+ Should be <2>. The first cell is the pin number (within the controller's
+ pin space), and the second is used for the following:
+ bit[0]: polarity (0 for active-high, 1 for active-low)
+
+- gpio-controller:
+ Specifies that the node is a GPIO controller.
+
+- brcm,gpio-bank-widths:
+ Number of GPIO lines for each bank. Number of elements must
+ correspond to number of banks suggested by the 'reg' property.
+
+Optional properties:
+
+- interrupts:
+ The interrupt shared by all GPIO lines for this controller.
+
+- interrupt-parent:
+ phandle of the parent interrupt controller
+
+- #interrupt-cells:
+ Should be <2>. The first cell is the GPIO number, the second should specify
+ flags. The following subset of flags is supported:
+ - bits[3:0] trigger type and level flags
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ Valid combinations are 1, 2, 3, 4, 8.
+ See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
+
+- interrupt-controller:
+ Marks the device node as an interrupt controller
+
+- interrupt-names:
+ The name of the IRQ resource used by this controller
+
+Example:
+ upg_gio: gpio@f040a700 {
+ #gpio-cells = <0x2>;
+ #interrupt-cells = <0x2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf040a700 0x80>;
+ interrupt-parent = <0xf>;
+ interrupts = <0x6>;
+ interrupt-names = "upg_gio";
+ brcm,gpio-bank-widths = <0x20 0x20 0x20 0x18>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt
new file mode 100644
index 000000000000..abf4db736c6e
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-etraxfs.txt
@@ -0,0 +1,21 @@
+Axis ETRAX FS General I/O controller bindings
+
+Required properties:
+
+- compatible:
+ - "axis,etraxfs-gio"
+- reg: Physical base address and length of the controller's registers.
+- #gpio-cells: Should be 3
+ - The first cell is the gpio offset number.
+ - The second cell is reserved and is currently unused.
+ - The third cell is the port number (hex).
+- gpio-controller: Marks the device node as a GPIO controller.
+
+Example:
+
+ gio: gpio@b001a000 {
+ compatible = "axis,etraxfs-gio";
+ reg = <0xb001a000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <3>;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-xlp.txt b/Documentation/devicetree/bindings/gpio/gpio-xlp.txt
new file mode 100644
index 000000000000..262ee4ddf2cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-xlp.txt
@@ -0,0 +1,47 @@
+Netlogic XLP Family GPIO
+========================
+
+This GPIO driver is used for following Netlogic XLP SoCs:
+ XLP832, XLP316, XLP208, XLP980, XLP532
+
+Required properties:
+-------------------
+
+- compatible: Should be one of the following:
+ - "netlogic,xlp832-gpio": For Netlogic XLP832
+ - "netlogic,xlp316-gpio": For Netlogic XLP316
+ - "netlogic,xlp208-gpio": For Netlogic XLP208
+ - "netlogic,xlp980-gpio": For Netlogic XLP980
+ - "netlogic,xlp532-gpio": For Netlogic XLP532
+- reg: Physical base address and length of the controller's registers.
+- #gpio-cells: Should be two. The first cell is the pin number and the second
+ cell is used to specify optional parameters (currently unused).
+- gpio-controller: Marks the device node as a GPIO controller.
+- nr-gpios: Number of GPIO pins supported by the controller.
+- interrupt-cells: Should be two. The first cell is the GPIO Number. The
+ second cell is used to specify flags. The following subset of flags is
+ supported:
+ - trigger type:
+ 1 = low to high edge triggered.
+ 2 = high to low edge triggered.
+ 4 = active high level-sensitive.
+ 8 = active low level-sensitive.
+- interrupts: Interrupt number for this device.
+- interrupt-parent: phandle of the parent interrupt controller.
+- interrupt-controller: Identifies the node as an interrupt controller.
+
+Example:
+
+ gpio: xlp_gpio@34000 {
+ compatible = "netlogic,xlp316-gpio";
+ reg = <0 0x34100 0x1000
+ 0 0x35100 0x1000>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ nr-gpios = <57>;
+
+ #interrupt-cells = <2>;
+ interrupt-parent = <&pic>;
+ interrupts = <39>;
+ interrupt-controller;
+ };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt
index 986371a4be2c..db4c6a663c03 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-zynq.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.txt
@@ -6,7 +6,7 @@ Required properties:
- First cell is the GPIO line number
- Second cell is used to specify optional
parameters (unused)
-- compatible : Should be "xlnx,zynq-gpio-1.0"
+- compatible : Should be "xlnx,zynq-gpio-1.0" or "xlnx,zynqmp-gpio-1.0"
- clocks : Clock specifier (see clock bindings for details)
- gpio-controller : Marks the device node as a GPIO controller.
- interrupts : Interrupt specifier (see interrupt bindings for
diff --git a/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt
new file mode 100644
index 000000000000..eb7cdd69e10b
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/nxp,lpc1850-gpio.txt
@@ -0,0 +1,39 @@
+NXP LPC18xx/43xx GPIO controller Device Tree Bindings
+-----------------------------------------------------
+
+Required properties:
+- compatible : Should be "nxp,lpc1850-gpio"
+- reg : Address and length of the register set for the device
+- clocks : Clock specifier (see clock bindings for details)
+- gpio-controller : Marks the device node as a GPIO controller.
+- #gpio-cells : Should be two
+ - First cell is the GPIO line number
+ - Second cell is used to specify polarity
+
+Optional properties:
+- gpio-ranges : Mapping between GPIO and pinctrl
+
+Example:
+#define LPC_GPIO(port, pin) (port * 32 + pin)
+#define LPC_PIN(port, pin) (0x##port * 32 + pin)
+
+gpio: gpio@400f4000 {
+ compatible = "nxp,lpc1850-gpio";
+ reg = <0x400f4000 0x4000>;
+ clocks = <&ccu1 CLK_CPU_GPIO>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl LPC_GPIO(0,0) LPC_PIN(0,0) 2>,
+ ...
+ <&pinctrl LPC_GPIO(7,19) LPC_PIN(f,5) 7>;
+};
+
+gpio_joystick {
+ compatible = "gpio-keys-polled";
+ ...
+
+ button@0 {
+ ...
+ gpios = <&gpio LPC_GPIO(4,8) GPIO_ACTIVE_LOW>;
+ };
+};
diff --git a/Documentation/gpio/consumer.txt b/Documentation/gpio/consumer.txt
index c21c1313f09e..bbc8b5888b80 100644
--- a/Documentation/gpio/consumer.txt
+++ b/Documentation/gpio/consumer.txt
@@ -241,18 +241,18 @@ Set multiple GPIO outputs with a single function call
-----------------------------------------------------
The following functions set the output values of an array of GPIOs:
- void gpiod_set_array(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_raw_array(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_array_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
- void gpiod_set_raw_array_cansleep(unsigned int array_size,
- struct gpio_desc **desc_array,
- int *value_array)
+ void gpiod_set_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_raw_array_value(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
+ void gpiod_set_raw_array_value_cansleep(unsigned int array_size,
+ struct gpio_desc **desc_array,
+ int *value_array)
The array can be an arbitrary set of GPIOs. The functions will try to set
GPIOs belonging to the same bank or chip simultaneously if supported by the
@@ -271,8 +271,8 @@ matches the desired group of GPIOs, those GPIOs can be set by simply using
the struct gpio_descs returned by gpiod_get_array():
struct gpio_descs *my_gpio_descs = gpiod_get_array(...);
- gpiod_set_array(my_gpio_descs->ndescs, my_gpio_descs->desc,
- my_gpio_values);
+ gpiod_set_array_value(my_gpio_descs->ndescs, my_gpio_descs->desc,
+ my_gpio_values);
It is also possible to set a completely arbitrary array of descriptors. The
descriptors may be obtained using any combination of gpiod_get() and
diff --git a/Documentation/gpio/gpio-legacy.txt b/Documentation/gpio/gpio-legacy.txt
index 6f83fa965b4b..79ab5648d69b 100644
--- a/Documentation/gpio/gpio-legacy.txt
+++ b/Documentation/gpio/gpio-legacy.txt
@@ -751,9 +751,6 @@ requested using gpio_request():
int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
- /* change the polarity of a GPIO node in sysfs */
- int gpio_sysfs_set_active_low(unsigned gpio, int value);
-
After a kernel driver requests a GPIO, it may only be made available in
the sysfs interface by gpio_export(). The driver can control whether the
signal direction may change. This helps drivers prevent userspace code
@@ -767,9 +764,3 @@ After the GPIO has been exported, gpio_export_link() allows creating
symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can
use this to provide the interface under their own device in sysfs with
a descriptive name.
-
-Drivers can use gpio_sysfs_set_active_low() to hide GPIO line polarity
-differences between boards from user space. This only affects the
-sysfs interface. Polarity change can be done both before and after
-gpio_export(), and previously enabled poll(2) support for either
-rising or falling edge will be reconfigured to follow this setting.
diff --git a/Documentation/gpio/sysfs.txt b/Documentation/gpio/sysfs.txt
index c2c3a97f8ff7..535b6a8a7a7c 100644
--- a/Documentation/gpio/sysfs.txt
+++ b/Documentation/gpio/sysfs.txt
@@ -132,9 +132,6 @@ requested using gpio_request():
int gpiod_export_link(struct device *dev, const char *name,
struct gpio_desc *desc);
- /* change the polarity of a GPIO node in sysfs */
- int gpiod_sysfs_set_active_low(struct gpio_desc *desc, int value);
-
After a kernel driver requests a GPIO, it may only be made available in
the sysfs interface by gpiod_export(). The driver can control whether the
signal direction may change. This helps drivers prevent userspace code
@@ -148,8 +145,3 @@ After the GPIO has been exported, gpiod_export_link() allows creating
symlinks from elsewhere in sysfs to the GPIO sysfs node. Drivers can
use this to provide the interface under their own device in sysfs with
a descriptive name.
-
-Drivers can use gpiod_sysfs_set_active_low() to hide GPIO line polarity
-differences between boards from user space. Polarity change can be done both
-before and after gpiod_export(), and previously enabled poll(2) support for
-either rising or falling edge will be reconfigured to follow this setting.
diff --git a/Documentation/zh_CN/gpio.txt b/Documentation/zh_CN/gpio.txt
index d5b8f01833f4..bce972521065 100644
--- a/Documentation/zh_CN/gpio.txt
+++ b/Documentation/zh_CN/gpio.txt
@@ -638,9 +638,6 @@ GPIO 控制器的路径类似 /sys/class/gpio/gpiochip42/ (对于从#42 GPIO
int gpio_export_link(struct device *dev, const char *name,
unsigned gpio)
- /* 改变 sysfs 中的一个 GPIO 节点的极性 */
- int gpio_sysfs_set_active_low(unsigned gpio, int value);
-
在一个内核驱动申请一个 GPIO 之后,它可以通过 gpio_export()使其在 sysfs
接口中可见。该驱动可以控制信号方向是否可修改。这有助于防止用户空间代码无意间
破坏重要的系统状态。
@@ -651,8 +648,3 @@ GPIO 控制器的路径类似 /sys/class/gpio/gpiochip42/ (对于从#42 GPIO
在 GPIO 被导出之后,gpio_export_link()允许在 sysfs 文件系统的任何地方
创建一个到这个 GPIO sysfs 节点的符号链接。这样驱动就可以通过一个描述性的
名字,在 sysfs 中他们所拥有的设备下提供一个(到这个 GPIO sysfs 节点的)接口。
-
-驱动可以使用 gpio_sysfs_set_active_low() 来在用户空间隐藏电路板之间
-GPIO 线的极性差异。这个仅对 sysfs 接口起作用。极性的改变可以在 gpio_export()
-前后进行,且之前使能的轮询操作(poll(2))支持(上升或下降沿)将会被重新配置来遵循
-这个设置。