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authorBorislav Petkov <bp@suse.de>2016-01-13 16:48:51 +0100
committerJonathan Corbet <corbet@lwn.net>2016-01-14 13:24:54 -0700
commitafd8c08446d6503adc1ccd2726a8e27f35d95b79 (patch)
treebc0f9b31655f3f6659af6938908e552c3b8a65fc /Documentation
parent000afe892ed6ff127745e7ab4fba4bc52248d6f4 (diff)
Documentation: Explain pci=conf1,conf2 more verbosely
People complained that setting the PCI config space access mechanism through "pci=conf1" or "pci=conf2" on the command line is not really documented. Yeah, can you blame them? Look at what we have now. So try to improve the situation a bit by explaining what those "conf1" and "conf2" things actually mean. See http://wiki.osdev.org/PCI for more info. Suggested-by: Eric Morton <Eric.Morton@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> [jc: Added the above URL to the document too] Signed-off-by: Jonathan Corbet <corbet@lwn.net>
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/kernel-parameters.txt14
1 files changed, 10 insertions, 4 deletions
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 9b2970fd237b..5e80a9bb1f4f 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -2736,10 +2736,16 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
hardware access methods are allowed. Use this
if you experience crashes upon bootup and you
suspect they are caused by the BIOS.
- conf1 [X86] Force use of PCI Configuration
- Mechanism 1.
- conf2 [X86] Force use of PCI Configuration
- Mechanism 2.
+ conf1 [X86] Force use of PCI Configuration Access
+ Mechanism 1 (config address in IO port 0xCF8,
+ data in IO port 0xCFC, both 32-bit).
+ conf2 [X86] Force use of PCI Configuration Access
+ Mechanism 2 (IO port 0xCF8 is an 8-bit port for
+ the function, IO port 0xCFA, also 8-bit, sets
+ bus number. The config space is then accessed
+ through ports 0xC000-0xCFFF).
+ See http://wiki.osdev.org/PCI for more info
+ on the configuration access mechanisms.
noaer [PCIE] If the PCIEAER kernel config parameter is
enabled, this kernel boot option can be used to
disable the use of PCIE advanced error reporting.