diff options
| author | Dinh Nguyen <dinguyen@kernel.org> | 2021-11-22 09:54:00 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2021-12-27 04:20:05 -0600 |
| commit | f34e8875ae244462711e31fcc4a82db13a16d36f (patch) | |
| tree | 847c5e68783fa96801ecb5ace0b2e28b6689e2fd /Documentation | |
| parent | fc74e0a40e4f9fd0468e34045b0c45bba11dcbb2 (diff) | |
dt-bindings: spi: cadence-quadspi: document "intel,socfpga-qspi"
The QSPI controller on Intel's SoCFPGA platform does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash.
Introduce the dts compatible "intel,socfpga-qspi" to differentiate the
hardware.
Acked-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v3: revert to "intel,socfpga-qspi"
v2: change binding to "cdns,qspi-nor-0010" to be more generic for other
platforms
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index ca155abbda7a..037f41f58503 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -29,6 +29,7 @@ properties: - ti,am654-ospi - intel,lgm-qspi - xlnx,versal-ospi-1.0 + - intel,socfpga-qspi - const: cdns,qspi-nor - const: cdns,qspi-nor |