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authorMark Brown <broonie@kernel.org>2022-11-01 11:27:14 +0000
committerMarc Zyngier <maz@kernel.org>2022-11-01 19:30:34 +0000
commitbe0ddf5293a7895a8c9096e1a8560930c6a0ab3f (patch)
tree0b2f3ec9464f614e62b04f98da2040ca3c2df9e6 /Documentation
parent4151bb636acf32bb2e6126cec8216b023117c0e9 (diff)
arm64: booting: Document our requirements for fine grained traps with SME
With SME we require that fine grained traps on access to TPIDR2_EL0 and SMPRI_EL1 are disabled but did not document that fact. Add the relevant register bits. Signed-off-by: Mark Brown <broonie@kernel.org> Reviewed-by: Oliver Upton <oliver.upton@linux.dev> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20221101112716.52035-2-broonie@kernel.org
Diffstat (limited to 'Documentation')
-rw-r--r--Documentation/arm64/booting.rst8
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst
index 8aefa1001ae5..8c324ad638de 100644
--- a/Documentation/arm64/booting.rst
+++ b/Documentation/arm64/booting.rst
@@ -340,6 +340,14 @@ Before jumping into the kernel, the following conditions must be met:
- SMCR_EL2.LEN must be initialised to the same value for all CPUs the
kernel will execute on.
+ - HWFGRTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
+
+ - HWFGWTR_EL2.nTPIDR2_EL0 (bit 55) must be initialised to 0b01.
+
+ - HWFGRTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
+
+ - HWFGWTR_EL2.nSMPRI_EL1 (bit 54) must be initialised to 0b01.
+
For CPUs with the Scalable Matrix Extension FA64 feature (FEAT_SME_FA64)
- If EL3 is present: