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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-09-06 11:58:15 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-09-06 11:58:15 -0700 |
| commit | 2ccdd9f8b2ce7290aad6f0a34200ad394e61f940 (patch) | |
| tree | 2213db3ad429c6dfe3563bb5446e1fa06e3add7c /MAINTAINERS | |
| parent | 015b3155c46a089f623c8a2e794ffad84143565d (diff) | |
| parent | 29aaebbca4abc4cceb38738483051abefafb6950 (diff) | |
Merge tag 'iommu-fixes-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
- three Intel VT-d fixes to fix address handling on 32bit, fix a NULL
pointer dereference bug and serialize a hardware register access as
required by the VT-d spec.
- two patches for AMD IOMMU to force AMD GPUs into translation mode
when memory encryption is active and disallow using IOMMUv2
functionality. This makes the AMDGPU driver work when memory
encryption is active.
- two more fixes for AMD IOMMU to fix updating the Interrupt Remapping
Table Entries.
- MAINTAINERS file update for the Qualcom IOMMU driver.
* tag 'iommu-fixes-v5.9-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/vt-d: Handle 36bit addressing for x86-32
iommu/amd: Do not use IOMMUv2 functionality when SME is active
iommu/amd: Do not force direct mapping when SME is active
iommu/amd: Use cmpxchg_double() when updating 128-bit IRTE
iommu/amd: Restore IRTE.RemapEn bit after programming IRTE
iommu/vt-d: Fix NULL pointer dereference in dev_iommu_priv_set()
iommu/vt-d: Serialize IOMMU GCMD register modifications
MAINTAINERS: Update QUALCOMM IOMMU after Arm SMMU drivers move
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index cef55acca692..b5cfab015bd6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14388,7 +14388,7 @@ M: Rob Clark <robdclark@gmail.com> L: iommu@lists.linux-foundation.org L: linux-arm-msm@vger.kernel.org S: Maintained -F: drivers/iommu/qcom_iommu.c +F: drivers/iommu/arm/arm-smmu/qcom_iommu.c QUALCOMM IPCC MAILBOX DRIVER M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> |