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authorVineet Gupta <vgupta@synopsys.com>2017-01-18 15:10:52 -0800
committerVineet Gupta <vgupta@synopsys.com>2017-01-18 19:21:02 -0800
commit76894a72a0d7e0759de272bf3f4d2279ebd86d0b (patch)
tree22c25454a849b11c9bdec4854ba4aa43d6e47de0 /arch/arc/mm/cache.c
parente497c8e52a83ebb5309ab41c8851c9cb53f28b73 (diff)
ARC: mm: split arc_cache_init to allow __init reaping of bulk
arc_cache_init() is called for each core so can't be tagged __init. However bulk of it is only executed by master core and thus is candidate for __init reaping. So split it up to allow that. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/cache.c')
-rw-r--r--arch/arc/mm/cache.c33
1 files changed, 19 insertions, 14 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index 3c275a81528c..ee01979e3d01 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -993,7 +993,7 @@ SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags)
* 3. All Caches need to be disabled when setting up IOC to elide any in-flight
* Coherency transactions
*/
-noinline void arc_ioc_setup(void)
+noinline void __init arc_ioc_setup(void)
{
unsigned int ap_sz;
@@ -1023,21 +1023,9 @@ noinline void arc_ioc_setup(void)
__dc_enable();
}
-void arc_cache_init(void)
+void __init arc_cache_init_master(void)
{
unsigned int __maybe_unused cpu = smp_processor_id();
- char str[256];
-
- printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
-
- /*
- * Only master CPU needs to execute rest of function:
- * - Assume SMP so all cores will have same cache config so
- * any geomtry checks will be same for all
- * - IOC setup / dma callbacks only need to be setup once
- */
- if (cpu)
- return;
if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) {
struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache;
@@ -1106,3 +1094,20 @@ void arc_cache_init(void)
__dma_cache_wback = __dma_cache_wback_l1;
}
}
+
+void __ref arc_cache_init(void)
+{
+ unsigned int __maybe_unused cpu = smp_processor_id();
+ char str[256];
+
+ printk(arc_cache_mumbojumbo(0, str, sizeof(str)));
+
+ /*
+ * Only master CPU needs to execute rest of function:
+ * - Assume SMP so all cores will have same cache config so
+ * any geomtry checks will be same for all
+ * - IOC setup / dma callbacks only need to be setup once
+ */
+ if (!cpu)
+ arc_cache_init_master();
+}