diff options
| author | Vineet Gupta <vgupta@synopsys.com> | 2013-08-23 17:37:18 +0530 |
|---|---|---|
| committer | Vineet Gupta <vgupta@synopsys.com> | 2013-08-30 21:42:18 +0530 |
| commit | 5bd87adf9b2ae5fa1bb469c68029b4eec06d6e03 (patch) | |
| tree | 25b80c5717ae313fa52d4153caa6fef3100055bb /arch/arc/mm/tlbex.S | |
| parent | ade922f8e269115252d199bf6c524a10379cf716 (diff) | |
ARC: [ASID] Refactor the TLB paranoid debug code
-Asm code already has values of SW and HW ASID values, so they can be
passed to the printing routine.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/mm/tlbex.S')
| -rw-r--r-- | arch/arc/mm/tlbex.S | 16 |
1 files changed, 7 insertions, 9 deletions
diff --git a/arch/arc/mm/tlbex.S b/arch/arc/mm/tlbex.S index 50e83ca96b96..88897a112d55 100644 --- a/arch/arc/mm/tlbex.S +++ b/arch/arc/mm/tlbex.S @@ -102,7 +102,7 @@ ex_saved_reg1: ; VERIFY if the ASID in MMU-PID Reg is same as ; one in Linux data structures - DBG_ASID_MISMATCH + tlb_paranoid_check_asm .endm .macro TLBMISS_RESTORE_REGS @@ -133,34 +133,32 @@ ex_saved_reg1: ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble. ; So we try to detect this in TLB Mis shandler - -.macro DBG_ASID_MISMATCH +.macro tlb_paranoid_check_asm #ifdef CONFIG_ARC_DBG_TLB_PARANOIA - ; make sure h/w ASID is same as s/w ASID - GET_CURR_TASK_ON_CPU r3 ld r0, [r3, TASK_ACT_MM] ld r0, [r0, MM_CTXT+MM_CTXT_ASID] lr r1, [ARC_REG_PID] and r1, r1, 0xFF + breq r1, r0, 5f ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode - lr r0, [erstatus] - bbit0 r0, STATUS_U_BIT, 5f + lr r2, [erstatus] + bbit0 r2, STATUS_U_BIT, 5f ; We sure are in troubled waters, Flag the error, but to do so ; need to switch to kernel mode stack to call error routine GET_TSK_STACK_BASE r3, sp ; Call printk to shoutout aloud - mov r0, 1 + mov r2, 1 j print_asid_mismatch -5: ; ASIDs match so proceed normally +5: ; ASIDs match so proceed normally nop #endif |