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authorVineet Gupta <vgupta@synopsys.com>2017-01-04 12:02:44 -0800
committerVineet Gupta <vgupta@synopsys.com>2017-01-04 17:12:09 -0800
commitfa84d7310d19e0b77979019df82e357b1e8443e3 (patch)
treea076e135e1563e19f9958f3400437cf7724f4148 /arch/arc
parent7ce7d89f48834cefece7804d38fc5d85382edf77 (diff)
ARC: mmu: clarify the MMUv3 programming model
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc')
-rw-r--r--arch/arc/mm/cache.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/arc/mm/cache.c b/arch/arc/mm/cache.c
index ec86ac0e3321..6d98e1d57a18 100644
--- a/arch/arc/mm/cache.c
+++ b/arch/arc/mm/cache.c
@@ -271,7 +271,11 @@ void __cache_line_loop_v2(phys_addr_t paddr, unsigned long vaddr,
/*
* For ARC700 MMUv3 I-cache and D-cache flushes
- * Also reused for HS38 aliasing I-cache configuration
+ * - ARC700 programming model requires paddr and vaddr be passed in seperate
+ * AUX registers (*_IV*L and *_PTAG respectively) irrespective of whether the
+ * caches actually alias or not.
+ * - For HS38, only the aliasing I-cache configuration uses the PTAG reg
+ * (non aliasing I-cache version doesn't; while D-cache can't possibly alias)
*/
static inline
void __cache_line_loop_v3(phys_addr_t paddr, unsigned long vaddr,