diff options
| author | Nick Hawkins <nick.hawkins@hpe.com> | 2022-05-18 14:38:37 +0100 |
|---|---|---|
| committer | Russell King (Oracle) <rmk+kernel@armlinux.org.uk> | 2022-05-20 12:33:48 +0100 |
| commit | 8294fec1cab7ae6153525eb68401ed5905921371 (patch) | |
| tree | 033303ff64cb5ad496c0b746267c2110c4c0f31b /arch/arm/Kconfig | |
| parent | ad12c2f1587c6ec9b52ff226f438955bfae6ad89 (diff) | |
ARM: 9206/1: A9: Add ARM ERRATA 764319 workaround (Updated)
Enable the workaround for the 764319 Cortex A-9 erratum.
CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
unexpected Undefined Instruction exception when the DBGSWENABLE external
pin is set to 0, even when the CP14 accesses are performed from a
privileged mode. The work around catches the exception in a way
the kernel does not stop execution with the use of undef_hook. This
has been found to effect the HPE GXP SoC.
Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 2e8091e2d8a8..0dcf88e7f9cf 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -972,6 +972,17 @@ config ARM_ERRATA_764369 relevant cache maintenance functions and sets a specific bit in the diagnostic control register of the SCU. +config ARM_ERRATA_764319 + bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" + depends on CPU_V7 + help + This option enables the workaround for the 764319 Cortex A-9 erratum. + CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an + unexpected Undefined Instruction exception when the DBGSWENABLE + external pin is set to 0, even when the CP14 accesses are performed + from a privileged mode. This work around catches the exception in a + way the kernel does not stop execution. + config ARM_ERRATA_775420 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" depends on CPU_V7 |