summaryrefslogtreecommitdiff
path: root/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
diff options
context:
space:
mode:
authorMatthew Hagan <mnhagan88@gmail.com>2021-08-06 21:44:35 +0100
committerFlorian Fainelli <f.fainelli@gmail.com>2021-09-14 14:34:53 -0700
commitaf413758ea718b0c92b1a0ad5a374eff6db255df (patch)
treeaf8cb7d38035b9a79b3636e63400d067f24bf974 /arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
parentd50a0923f35baad084c093506d7688699558c272 (diff)
ARM: dts: NSP: Add DT files for Meraki MX65 series
MX65 & MX65W Hardware info: - CPU: Broadcom BCM58625 Cortex A9 @ 1200Mhz - RAM: 2 GB (4 x 4Gb SK Hynix H5TC4G83CFR) - Storage: 1 GB (Micron MT29F8G08ABACA) - Networking: BCM58625 switch (2x 1GbE ports) 2x Qualcomm QCA8337 switches (10x 1GbE ports total) - PSE: Broadcom BCM59111KMLG connected to LAN ports 11 & 12 - USB: 1x USB2.0 - Serial: Internal header - WLAN(MX65W Only): 2x Broadcom BCM43520KMLG on the PCI bus. Note that a driver and firmware image for the BCM59111 PSE has been released under GPL, but this is not present in the kernel. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Diffstat (limited to 'arch/arm/boot/dts/bcm958625-meraki-mx65w.dts')
-rw-r--r--arch/arm/boot/dts/bcm958625-meraki-mx65w.dts32
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
new file mode 100644
index 000000000000..a2165aba3676
--- /dev/null
+++ b/arch/arm/boot/dts/bcm958625-meraki-mx65w.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Device Tree Bindings for Cisco Meraki MX65W.
+ *
+ * Copyright (C) 2020-2021 Matthew Hagan <mnhagan88@gmail.com>
+ */
+
+/dts-v1/;
+
+#include "bcm958625-meraki-alamo.dtsi"
+
+/ {
+ model = "Cisco Meraki MX65W";
+ compatible = "meraki,mx65w", "brcm,bcm58625", "brcm,nsp";
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x80000000>;
+ };
+};
+
+&pcie0 {
+ status = "okay";
+};
+
+&pcie1 {
+ status = "okay";
+};