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authorArnd Bergmann <arnd@arndb.de>2016-11-30 15:18:48 +0100
committerArnd Bergmann <arnd@arndb.de>2016-11-30 15:18:48 +0100
commitaea09e58417f5207e930aceaaef4c923a0506a43 (patch)
tree977628109a44d92cc768b7a0e0c788b2144dcbe4 /arch/arm/boot/dts/da850.dtsi
parentd0bf34f39b7ee3f040da0a9be7ed5e169936c578 (diff)
parent83de086cc89410a8d4e0b6345e8a1116797ea703 (diff)
Merge tag 'davinci-for-v4.10/dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/dt
Pull "DaVinci DT updates for v4.10 (part 2)" from Sekhar Nori: Adds device tree nodes enabling DDR controller and bus master priority settings needed for stable LCDC operation on DA850. Also adds support for MUSB device on DA850 providing USB OTG support. * tag 'davinci-for-v4.10/dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci: ARM: dts: da850-lcdk: Enable the usb otg device node ARM: dts: da850: Add the usb otg device node ARM: dts: da850: add the mstpri and ddrctl nodes
Diffstat (limited to 'arch/arm/boot/dts/da850.dtsi')
-rw-r--r--arch/arm/boot/dts/da850.dtsi18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 1bb1f6d7c99a..ff13e95af298 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -210,6 +210,10 @@
};
};
+ prictrl: priority-controller@14110 {
+ compatible = "ti,da850-mstpri";
+ reg = <0x14110 0x0c>;
+ };
cfgchip: chip-controller@1417c {
compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
reg = <0x1417c 0x14>;
@@ -384,6 +388,16 @@
dma-names = "rx", "tx";
status = "disabled";
};
+ usb0: usb@200000 {
+ compatible = "ti,da830-musb";
+ reg = <0x200000 0x10000>;
+ interrupts = <58>;
+ interrupt-names = "mc";
+ dr_mode = "otg";
+ phys = <&usb_phy 0>;
+ phy-names = "usb-phy";
+ status = "disabled";
+ };
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
@@ -451,4 +465,8 @@
1 0 0x68000000 0x00008000>;
status = "disabled";
};
+ memctrl: memory-controller@b0000000 {
+ compatible = "ti,da850-ddr-controller";
+ reg = <0xb0000000 0xe8>;
+ };
};