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authorOlof Johansson <olof@lixom.net>2018-01-04 23:06:32 -0800
committerOlof Johansson <olof@lixom.net>2018-01-04 23:06:32 -0800
commit38b45e518655f8334b395ebe0be4ac238f598e3d (patch)
tree34d671cb38c6d2ea8b81eea2ed7022d6b63bc580 /arch/arm/boot/dts/dra7.dtsi
parent8db4e1faac7462e371364978dbe357c1c22e9e40 (diff)
parent1cadb0c341079785182a8d00d12ecb0bbef935fb (diff)
Merge tag 'omap-for-v4.16/dt-pt2-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt
Second set of device tree changes for omaps for v4.16 merge window This branch mostly configures more hardware support: - Clean-up dts files to remove leading 0x and 0s from binding notation to remove more dtc compiler warnings - A series of am437x updates for backlight, to fix inverted pad pull macro, and to configure power management related OPPs - Configure n950 and droid 4 command mode LCD panels - Updates to pandora and gta04 LCD panels - Add support for am574x-idk - A series of changes to configure more dra7 related PCIe features - A series of fixes for am335x-boneblue for WLAN, UARTs and CAN configuration - A series of changes to configure dra7 OPPs and VDD supplies * tag 'omap-for-v4.16/dt-pt2-v2-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (29 commits) Revert "ARM: dts: dra7: Add properties to enable PCIe x2 lane mode" ARM: dts: am572x-idk: Add cpu0 vdd supply ARM: dts: am571x-idk: Add cpu0 vdd supply ARM: dts: dra72-evm-tps65917: Add cpu0 vdd supply ARM: dts: dra7-evm: Add cpu0 vdd supply ARM: dts: am57xx-beagle-x15-common: Add cpu0 vdd supply ARM: dts: dra7: Enable 1.5 GHz operation for the CPU ARM: dts: dra7: Add MPU OPP supply node ARM: dts: dra7: Add vbb-supply to cpu and additional voltages ARM: dts: am335x-boneblue: enable can ARM: dts: am335x-boneblue: enable usarts ARM: dts: am335x-boneblue: fix wl1835 IRQ pin ARM: dts: dra7: Remove deprecated PCI compatible string ARM: dts: dra76-evm: Enable x2 PCIe lanes ARM: dts: DRA72x: Use PCIe compatible specific to dra72 ARM: dts: DRA74x: Use PCIe compatible specific to dra74 ARM: dts: dra7: Add properties to enable PCIe x2 lane mode ARM: dts: am57xx: Add support for am574x-idk ARM: dts: am43x-epos-evm: Hook dcdc2 as the cpu0-supply ARM: dts: am437x-idk-evm: Disable OPP50 for MPU ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
-rw-r--r--arch/arm/boot/dts/dra7.dtsi36
1 files changed, 29 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 3c8c0d743dd0..aabb86663f11 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -93,6 +93,8 @@
cooling-min-level = <0>;
cooling-max-level = <2>;
#cooling-cells = <2>; /* min followed by max */
+
+ vbb-supply = <&abb_mpu>;
};
};
@@ -102,16 +104,26 @@
opp_nom-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
- opp-microvolt = <1060000 850000 1150000>;
+ opp-microvolt = <1060000 850000 1150000>,
+ <1060000 850000 1150000>;
opp-supported-hw = <0xFF 0x01>;
opp-suspend;
};
opp_od-1176000000 {
opp-hz = /bits/ 64 <1176000000>;
- opp-microvolt = <1160000 885000 1160000>;
+ opp-microvolt = <1160000 885000 1160000>,
+ <1160000 885000 1160000>;
+
opp-supported-hw = <0xFF 0x02>;
};
+
+ opp_high@1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <1210000 950000 1250000>,
+ <1210000 950000 1250000>;
+ opp-supported-hw = <0xFF 0x04>;
+ };
};
/*
@@ -304,7 +316,6 @@
* node and enable pcie1_ep mode.
*/
pcie1_rc: pcie@51000000 {
- compatible = "ti,dra7-pcie";
reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 232 0x4>, <0 233 0x4>;
@@ -334,7 +345,6 @@
};
pcie1_ep: pcie_ep@51000000 {
- compatible = "ti,dra7-pcie-ep";
reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
interrupts = <0 232 0x4>;
@@ -356,8 +366,7 @@
ranges = <0x51800000 0x51800000 0x3000
0x0 0x30000000 0x10000000>;
status = "disabled";
- pcie@51800000 {
- compatible = "ti,dra7-pcie";
+ pcie2_rc: pcie@51800000 {
reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
reg-names = "rc_dbics", "ti_conf", "config";
interrupts = <0 355 0x4>, <0 356 0x4>;
@@ -1386,7 +1395,7 @@
ranges;
reg = <0x4a090000 0x20>;
ti,hwmods = "ocp2scp3";
- sata_phy: phy@4A096000 {
+ sata_phy: phy@4a096000 {
compatible = "ti,phy-pipe3-sata";
reg = <0x4A096000 0x80>, /* phy_rx */
<0x4A096400 0x64>, /* phy_tx */
@@ -2077,6 +2086,19 @@
clocks = <&l3_iclk_div>;
clock-names = "fck";
};
+
+ opp_supply_mpu: opp-supply@4a003b20 {
+ compatible = "ti,omap5-opp-supply";
+ reg = <0x4a003b20 0xc>;
+ ti,efuse-settings = <
+ /* uV offset */
+ 1060000 0x0
+ 1160000 0x4
+ 1210000 0x8
+ >;
+ ti,absolute-max-voltage-uv = <1500000>;
+ };
+
};
thermal_zones: thermal-zones {