diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2017-12-19 15:01:27 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2017-12-21 07:24:52 -0800 |
| commit | 4ece93c020e3ee19767b1c111be39fe7e32f8bf2 (patch) | |
| tree | b119582c116e01978b7a02e4364f973d9321e2df /arch/arm/boot/dts/dra7.dtsi | |
| parent | 704f423ce0b25b8e5edd924569ed5617a30614dd (diff) | |
ARM: dts: dra7: Add properties to enable PCIe x2 lane mode
ti,syscon-lane-sel and ti,syscon-lane-conf properties specific to enable
PCIe x2 lane mode are added here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index d8eb1632bbdf..24c104d1360a 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -309,6 +309,8 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie1_intc 1>, <0 0 0 2 &pcie1_intc 2>, @@ -334,6 +336,8 @@ phys = <&pcie1_phy>; phy-names = "pcie-phy0"; ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-lane-conf = <&scm_conf 0x558>; + ti,syscon-lane-sel = <&scm_conf_pcie 0x18>; status = "disabled"; }; }; |