diff options
| author | Vignesh R <vigneshr@ti.com> | 2018-09-25 10:51:51 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-09-28 10:26:01 -0700 |
| commit | 6d0af44a82be87c13f2320821e9fbb8b8cf5a56f (patch) | |
| tree | e952eef998e6c674aba5f8cff9c31ffb6db5782f /arch/arm/boot/dts/dra7.dtsi | |
| parent | 20bcd4a4d76d7474047ff4539e7d65b990bb2556 (diff) | |
ARM: dts: dra7: Fix up unaligned access setting for PCIe EP
Bit positions of PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE and
PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE in CTRL_CORE_SMA_SW_7 are
incorrectly documented in the TRM. In fact, the bit positions are
swapped. Update the DT bindings for PCIe EP to reflect the same.
Fixes: d23f3839fe97 ("ARM: dts: DRA7: Add pcie1 dt node for EP mode")
Cc: stable@vger.kernel.org
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index 160c1c454b9c..9136b3cf9a2c 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -354,7 +354,7 @@ ti,hwmods = "pcie1"; phys = <&pcie1_phy>; phy-names = "pcie-phy0"; - ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; + ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; status = "disabled"; }; }; |